[mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 and SWM16

[jkolek]

Summary

Fix disassembling of 16-bit microMIPS load and store word multiple instructions (LWM16 and SWM16).

[zoran.jovanovic]

LGTM

llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
                                           uint64_t Address,
                                           const void *Decoder);
 
 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
                                           unsigned Insn,
                                           uint64_t Address,
                                           const void *Decoder);
 
+static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
+                                               unsigned Insn,
+                                               uint64_t Address,
+                                               const void *Decoder);
+
 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
                                      unsigned Insn,
                                      uint64_t Address,
                                      const void *Decoder);
 
 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
                                      unsigned Insn,
                                      uint64_t Address,
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
 
   Inst.addOperand(MCOperand::CreateReg(Reg));
   Inst.addOperand(MCOperand::CreateReg(Mips::GP));
   Inst.addOperand(MCOperand::CreateImm(Offset << 2));
 
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
+                                               unsigned Insn,
+                                               uint64_t Address,
+                                               const void *Decoder) {
+  int Offset = SignExtend32<4>(Insn & 0xf);
+
+  if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
+      == MCDisassembler::Fail)
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::CreateReg(Mips::SP));
+  Inst.addOperand(MCOperand::CreateImm(Offset << 2));
+
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
                                      unsigned Insn,
                                      uint64_t Address,
                                      const void *Decoder) {
   int Offset = SignExtend32<12>(Insn & 0x0fff);
   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 
static DecodeStatus DecodeRegListOperand(MCInst &Inst,
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
                                            uint64_t Address,
                                            const void *Decoder) {
   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
-  unsigned RegNum;
-
   unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
-  // Empty register lists are not allowed.
-  if (RegLst == 0)
-    return MCDisassembler::Fail;
+  unsigned RegNum = RegLst & 0x3;
 
-  RegNum = RegLst & 0x3;
-  for (unsigned i = 0; i < RegNum - 1; i++)
+  for (unsigned i = 0; i <= RegNum; i++)
     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
 
   Inst.addOperand(MCOperand::CreateReg(Mips::RA));
 
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
                                      uint64_t Address, const void *Decoder) {
   Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2));
   return MCDisassembler::Success;
 }

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

class LoadMultMM<string opstr,
   let mayLoad = 1;
 }
 
 class StoreMultMM16<string opstr,
                     InstrItinClass Itin = NoItinerary,
                     ComplexPattern Addr = addr> :
   MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
                   !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
+  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
   let mayStore = 1;
 }
 
 class LoadMultMM16<string opstr,
                    InstrItinClass Itin = NoItinerary,
                    ComplexPattern Addr = addr> :
   MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
                   !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
+  let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
   let mayLoad = 1;
 }
 
 class UncondBranchMM16<string opstr> :
   MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
                   !strconcat(opstr, "\t$offset"),
                   [], IIBranch, FrmI> {
   let isBranch = 1;

llvm/trunk/test/MC/Disassembler/Mips/micromips.txt

 # CHECK: bnez16 $6, 20
 0xaf 0x0a
 
 # CHECK: b16 132
 0xcc 0x42
 
 # CHECK: lw $3, 32($gp)
 0x65 0x88
+
+# CHECK: lwm16 $16, $17, $ra, 8($sp)
+0x45 0x12
+
+# CHECK: swm16 $16, $17, $ra, 8($sp)
+0x45 0x52

llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt

 # CHECK: bnez16 $6, 20
 0x0a 0xaf
 
 # CHECK: b16 132
 0x42 0xcc
 
 # CHECK: lw $3, 32($gp)
 0x88 0x65
+
+# CHECK: lwm16 $16, $17, $ra, 8($sp)
+0x12 0x45
+
+# CHECK: swm16 $16, $17, $ra, 8($sp)
+0x52 0x45