[SystemZ] Add a subtarget cache like some other targets already have.

[jonpa]

Summary

Each function is with this compiled with the SystemZSubtarget initialized from the functions attributes.

We need the "+soft-float" feature in UsesVectorABI(), so we have the front end add it, so we don't need to check "-use-soft-float"="true", like the other targets, right?

[uweigand]

We need the "+soft-float" feature in UsesVectorABI(), so we have the front end add it, so we don't need to check "-use-soft-float"="true", like the other targets, right?

Yes, I think that's correct.

llvm/test/CodeGen/SystemZ/function-attributes-01.ll

11

Would be good to have some tests with "target-features"="-soft-float" as well.

30

This seems strange, an explicit per-function +soft-float should override the general setting, right?

63

Same here.

[jonpa]

Patch updated.

It seems that the general precedence (when invoking llc) is that first (in reverse order) is "target-features", and then -mattr. So for example a function with the attribute "target-features"="-vector" compiled with llc -mattr=+vector, gets a (SystemZTargetMachine::getSubtargetImpl) FS -vector,+vector, meaning that +vector wins.

It's interesting that the function attribute "target-cpu" seems to override the llc option -mcpu, while llc option -mattr= seems to override function attributes, like +-vector.

To get the behaviour you expected for soft-float (like also other targets seem to have), it seems easiest then to do like the other targets and check for the "use-soft-float"="true" attribute, and in that case add a final and decisive +soft-float to FS (this is not the way e.g. [+-]vector works per above, but maybe there is a reason for this?).

A function with "use-soft-float"="true" now always gets soft-float, while "use-soft-float"="false" will take no effect, so that -mattr=soft-float actually will give soft-float.

llvm/test/CodeGen/SystemZ/function-attributes-01.ll

11

I updated the tests to have "use-soft-float"="false" or "true", which is what all functions get from the clang front end.

[uweigand]

In D74086#1865011, @jonpa wrote:

It seems that the general precedence (when invoking llc) is that first (in reverse order) is "target-features", and then -mattr. So for example a function with the attribute "target-features"="-vector" compiled with llc -mattr=+vector, gets a (SystemZTargetMachine::getSubtargetImpl) FS -vector,+vector, meaning that +vector wins.

Huh, that seems unexpected. But as long as it's not a SystemZ problem, I guess it's just the way it is ...

To get the behaviour you expected for soft-float (like also other targets seem to have), it seems easiest then to do like the other targets and check for the "use-soft-float"="true" attribute, and in that case add a final and decisive +soft-float to FS (this is not the way e.g. [+-]vector works per above, but maybe there is a reason for this?).

OK, let's just mirror what everybody else is doing, then.

Patch LGTM. Thanks!

llvm/lib/Target/SystemZ/SystemZTDC.cpp

 // Instructions that match rules 1-3 are considered unworthy of conversion
 // on their own (since a comparison instruction is superior), but are mapped
 // in the hopes of folding the result using rules 4 and 8-10 (likely removing
 // the original comparison in the process).
 //
 //===----------------------------------------------------------------------===//
 
 #include "SystemZ.h"
+#include "SystemZSubtarget.h"
 #include "llvm/ADT/MapVector.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/IRBuilder.h"
 #include "llvm/IR/InstIterator.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/IntrinsicsS390.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/IR/Module.h"

 class SystemZTDCPass : public FunctionPass {
 public:
   static char ID;
   SystemZTDCPass() : FunctionPass(ID) {
     initializeSystemZTDCPassPass(*PassRegistry::getPassRegistry());
   }
 
   bool runOnFunction(Function &F) override;
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.addRequired<TargetPassConfig>();
+ }
+
 private:
   // Maps seen instructions that can be mapped to a TDC, values are
   // (TDC operand, TDC mask, worthy flag) triples.
   MapVector<Instruction *, std::tuple<Value *, int, bool>> ConvertedInsts;
   // The queue of and/or/xor i1 instructions to be potentially folded.
   std::vector<BinaryOperator *> LogicOpsWorklist;
   // Instructions matched while folding, to be removed at the end if unused.
   std::set<Instruction *> PossibleJunk;
case Instruction::Xor:
       break;
     default:
       llvm_unreachable("Unknown op in convertLogicOp");
   }
   converted(&I, Op0, Mask, true);
 }
 
 bool SystemZTDCPass::runOnFunction(Function &F) {
+  auto &TPC = getAnalysis<TargetPassConfig>();
+  if (TPC.getTM<TargetMachine>()
+          .getSubtarget<SystemZSubtarget>(F)
+          .hasSoftFloat())
+    return false;
+
   ConvertedInsts.clear();
   LogicOpsWorklist.clear();
   PossibleJunk.clear();
 
   // Look for icmp+fcmp instructions.
   for (auto &I : instructions(F)) {
     if (I.getOpcode() == Instruction::FCmp)
       convertFCmp(cast<CmpInst>(I));

llvm/lib/Target/SystemZ/SystemZTargetMachine.h

 #include "llvm/Support/CodeGen.h"
 #include "llvm/Target/TargetMachine.h"
 #include <memory>
 
 namespace llvm {
 
 class SystemZTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
-  SystemZSubtarget Subtarget;
+
+  mutable StringMap<std::unique_ptr<SystemZSubtarget>> SubtargetMap;
 
 public:
   SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,
                        Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
                        CodeGenOpt::Level OL, bool JIT);
   ~SystemZTargetMachine() override;
 
-  const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; }
-
-  const SystemZSubtarget *getSubtargetImpl(const Function &) const override {
-    return &Subtarget;
-  }
+  const SystemZSubtarget *getSubtargetImpl(const Function &) const override;
+  // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
+  // subtargets are per-function entities based on the target-specific
+  // attributes of each function.
+  const SystemZSubtarget *getSubtargetImpl() const = delete;
 
   // Override LLVMTargetMachine
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
   TargetTransformInfo getTargetTransformInfo(const Function &F) override;
 
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
 
   bool targetSchedulesPostRAScheduling() const override { return true; };
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZTARGETMACHINE_H

llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp

SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
                                            Optional<Reloc::Model> RM,
                                            Optional<CodeModel::Model> CM,
                                            CodeGenOpt::Level OL, bool JIT)
     : LLVMTargetMachine(
           T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
           getEffectiveRelocModel(RM),
           getEffectiveSystemZCodeModel(CM, getEffectiveRelocModel(RM), JIT),
           OL),
-      TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
-      Subtarget(TT, std::string(CPU), std::string(FS), *this) {
+      TLOF(std::make_unique<TargetLoweringObjectFileELF>()) {
   initAsmInfo();
 }
 
 SystemZTargetMachine::~SystemZTargetMachine() = default;
 
+const SystemZSubtarget *
+SystemZTargetMachine::getSubtargetImpl(const Function &F) const {
+  Attribute CPUAttr = F.getFnAttribute("target-cpu");
+  Attribute FSAttr = F.getFnAttribute("target-features");
+
+  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
+                        ? CPUAttr.getValueAsString().str()
+                        : TargetCPU;
+  std::string FS = !FSAttr.hasAttribute(Attribute::None)
+                       ? FSAttr.getValueAsString().str()
+                       : TargetFS;
+
+  // Since the (SystemZ) front end already has added "+soft-float" as a
+  // target feature, we don't need to add it again based on the
+  // "use-soft-float" attribute.
+
+  auto &I = SubtargetMap[CPU + FS];
+  if (!I) {
+    // This needs to be done before we create a new subtarget since any
+    // creation will depend on the TM and the code generation flags on the
+    // function that reside in TargetOptions.
+    resetTargetOptions(F);
+    I = std::make_unique<SystemZSubtarget>(TargetTriple, CPU, FS, *this);
+  }
+
+  return I.get();
+}
+
 namespace {
 
 /// SystemZ Code Generator Pass Configuration Options.
 class SystemZPassConfig : public TargetPassConfig {
 public:
   SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM)
     : TargetPassConfig(TM, PM) {}
 
public:
   void addPreSched2() override;
   void addPreEmitPass() override;
 };
 
 } // end anonymous namespace
 
 void SystemZPassConfig::addIRPasses() {
   if (getOptLevel() != CodeGenOpt::None) {
-    if (!getTM<SystemZTargetMachine>().getSubtargetImpl()->hasSoftFloat())
-      addPass(createSystemZTDCPass());
     addPass(createLoopDataPrefetchPass());
   }
 
   TargetPassConfig::addIRPasses();
 }
 
 bool SystemZPassConfig::addInstSelector() {
   addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));

llvm/test/CodeGen/SystemZ/function-attributes-01.ll

+; RUN: llc < %s -mtriple=s390x-linux-gnu \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,DEFAULT
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=soft-float \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,SOFT-FLOAT
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=-soft-float \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,NO-SOFT-FL
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=-vector \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,NO-VECTOR
+;
+; Test per function attributes and command line arguments that override them.
+
+attributes #1 = { "target-cpu"="z14" "target-features"="+vector" }
+define double @fun1(double* %A) #1 {
+; CHECK-LABEL: fun1:
+; DEFAULT:     ld %f0, 0(%r2)
+; SOFT-FLOAT:  lg %r2, 0(%r2)
+; NO-SOFT-FL:  ld %f0, 0(%r2)
+; NO-VECTOR:   ld %f0, 0(%r2)
+; CHECK-NEXT:  br %r14
+entry:
+  %0 = load double, double* %A
+  ret double %0
+}
+
+attributes #2 = { "target-cpu"="z14" "target-features"="+soft-float,+vector" }
+define double @fun2(double* %A) #2 {
+; CHECK-LABEL: fun2:
+; DEFAULT:     lg %r2, 0(%r2)
+; SOFT-FLOAT:  lg %r2, 0(%r2)
+; NO-SOFT-FL:  ld %f0, 0(%r2)
+; NO-VECTOR:   lg %r2, 0(%r2)
+; CHECK-NEXT:  br %r14
+entry:
+  %0 = load double, double* %A
+  ret double %0
+}
+
+attributes #3 = { "target-cpu"="z14" "target-features"="+vector" }
+define <2 x double> @fun3(<2 x double>* %A) #3 {
+; CHECK-LABEL:     fun3:
+; DEFAULT:         vl %v24, 0(%r2), 4
+; SOFT-FLOAT:      lg %r0, 0(%r2)
+; SOFT-FLOAT-NEXT: lg %r3, 8(%r2)
+; SOFT-FLOAT-NEXT: lgr %r2, %r0
+; NO-SOFT-FL:      vl %v24, 0(%r2), 4
+; NO-VECTOR:       ld %f0, 0(%r2)
+; NO-VECTOR-NEXT:  ld %f2, 8(%r2)
+; CHECK-NEXT:      br %r14
+entry:
+  %0 = load <2 x double>, <2 x double>* %A
+  ret <2 x double> %0
+}
+
+attributes #4 = { "target-cpu"="z14" "target-features"="+soft-float,+vector" }
+define <2 x double> @fun4(<2 x double>* %A) #4 {
+; CHECK-LABEL:     fun4:
+; DEFAULT:         lg %r0, 0(%r2)
+; DEFAULT-NEXT:    lg %r3, 8(%r2)
+; DEFAULT-NEXT:    lgr %r2, %r0
+; SOFT-FLOAT:      lg %r0, 0(%r2)
+; SOFT-FLOAT-NEXT: lg %r3, 8(%r2)
+; SOFT-FLOAT-NEXT: lgr %r2, %r0
+; NO-SOFT-FL:      vl %v24, 0(%r2), 4
+; NO-VECTOR:       lg %r0, 0(%r2)
+; NO-VECTOR-NEXT:  lg %r3, 8(%r2)
+; NO-VECTOR-NEXT:  lgr %r2, %r0
+; CHECK-NEXT:      br %r14
+entry:
+  %0 = load <2 x double>, <2 x double>* %A
+  ret <2 x double> %0
+}
+
+attributes #5 = { "target-cpu"="z14" "target-features"="-vector" }
+define <2 x double> @fun5(<2 x double>* %A) #5 {
+; CHECK-LABEL:     fun5:
+; DEFAULT:         ld %f0, 0(%r2)
+; DEFAULT-NEXT:    ld %f2, 8(%r2)
+; SOFT-FLOAT:      lg %r0, 0(%r2)
+; SOFT-FLOAT-NEXT: lg %r3, 8(%r2)
+; SOFT-FLOAT-NEXT: lgr %r2, %r0
+; NO-SOFT-FL:      ld %f0, 0(%r2)
+; NO-SOFT-FL-NEXT: ld %f2, 8(%r2)
+; NO-VECTOR:       ld %f0, 0(%r2)
+; NO-VECTOR-NEXT:  ld %f2, 8(%r2)
+; CHECK-NEXT:      br %r14
+entry:
+  %0 = load <2 x double>, <2 x double>* %A
+  ret <2 x double> %0
+}
+
+attributes #6 = { "target-cpu"="zEC12" }
+define <2 x double> @fun6(<2 x double>* %A) #6 {
+; CHECK-LABEL:     fun6:
+; DEFAULT:         ld %f0, 0(%r2)
+; DEFAULT-NEXT:    ld %f2, 8(%r2)
+; SOFT-FLOAT:      lg %r0, 0(%r2)
+; SOFT-FLOAT-NEXT: lg %r3, 8(%r2)
+; SOFT-FLOAT-NEXT: lgr %r2, %r0
+; NO-SOFT-FL:      ld %f0, 0(%r2)
+; NO-SOFT-FL-NEXT: ld %f2, 8(%r2)
+; NO-VECTOR:       ld %f0, 0(%r2)
+; NO-VECTOR-NEXT:  ld %f2, 8(%r2)
+; CHECK-NEXT:      br %r14
+entry:
+  %0 = load <2 x double>, <2 x double>* %A
+  ret <2 x double> %0
+}
+
+attributes #7 = { "target-cpu"="zEC12" "target-features"="+vector"}
+define <2 x double> @fun7(<2 x double>* %A) #7 {
+; CHECK-LABEL:     fun7:
+; DEFAULT:         vl %v24, 0(%r2), 4
+; SOFT-FLOAT:      lg %r0, 0(%r2)
+; SOFT-FLOAT-NEXT: lg %r3, 8(%r2)
+; SOFT-FLOAT-NEXT: lgr %r2, %r0
+; NO-SOFT-FL:      vl %v24, 0(%r2), 4
+; NO-VECTOR:       ld %f0, 0(%r2)
+; NO-VECTOR-NEXT:  ld %f2, 8(%r2)
+; CHECK-NEXT:      br %r14
+entry:
+  %0 = load <2 x double>, <2 x double>* %A
+  ret <2 x double> %0
+}