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Differential D74040

[ARM] Correct syntax of the CLRM insn
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Authored by chill on Feb 5 2020, 4:40 AM.

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simon_tatham
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rGa328536c6d7a: [ARM] Correct syntax of the CLRM insn
Summary

The predicate should be adjacent to the opcode.

Diff Detail

Event Timeline

chill created this revision.Feb 5 2020, 4:40 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 5 2020, 4:41 AM
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simon_tatham requested changes to this revision.Feb 5 2020, 4:57 AM
This revision now requires changes to proceed.Feb 5 2020, 4:57 AM
simon_tatham added inline comments.Feb 5 2020, 4:58 AM
llvm/lib/Target/ARM/ARMInstrThumb2.td
5210

This will generate an AsmString with two consecutive tab characters, because the V8_1MI base class inserts a \t between the asm and ops parameters, but you've put an extra \t in the ops string.

(I guess FileCheck normalizes out whitespace and so the test doesn't notice the difference.)

chill updated this revision to Diff 242575.Feb 5 2020, 5:50 AM
chill marked an inline comment as done.
simon_tatham accepted this revision.Feb 5 2020, 5:51 AM
This revision is now accepted and ready to land.Feb 5 2020, 5:51 AM
Closed by commit rGa328536c6d7a: [ARM] Correct syntax of the CLRM insn (authored by chill). · Explain WhyFeb 5 2020, 5:59 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
2 lines
test/
MC/
Disassembler/
ARM/
5 lines

Diff 242580

llvm/lib/Target/ARM/ARMInstrThumb2.td

Show First 20 Lines • Show All 5,201 Lines • ▼ Show 20 Lines
class V8_1MI<dag oops, dag iops, AddrMode am, InstrItinClass itin, string asm, class V8_1MI<dag oops, dag iops, AddrMode am, InstrItinClass itin, string asm,
string ops, string cstr, list<dag> pattern> string ops, string cstr, list<dag> pattern>
: Thumb2XI<oops, iops, am, 4, itin, !strconcat(asm, "\t", ops), cstr, : Thumb2XI<oops, iops, am, 4, itin, !strconcat(asm, "\t", ops), cstr,
pattern>, pattern>,
Requires<[HasV8_1MMainline]>; Requires<[HasV8_1MMainline]>;
def t2CLRM : V8_1MI<(outs), def t2CLRM : V8_1MI<(outs),
(ins pred:$p, reglist_with_apsr:$regs, variable_ops), (ins pred:$p, reglist_with_apsr:$regs, variable_ops),
AddrModeNone, NoItinerary, "clrm", "${p}\t$regs", "", []> { AddrModeNone, NoItinerary, "clrm${p}", "$regs", "", []> {
simon_tathamUnsubmitted
Done
ReplyInline Actions

This will generate an AsmString with two consecutive tab characters, because the V8_1MI base class inserts a \t between the asm and ops parameters, but you've put an extra \t in the ops string.

(I guess FileCheck normalizes out whitespace and so the test doesn't notice the difference.)

simon_tatham: This will generate an `AsmString` with two consecutive tab characters, because the `V8_1MI`…
bits<16> regs; bits<16> regs;
let Inst{31-16} = 0b1110100010011111; let Inst{31-16} = 0b1110100010011111;
let Inst{15-14} = regs{15-14}; let Inst{15-14} = regs{15-14};
let Inst{13} = 0b0; let Inst{13} = 0b0;
let Inst{12-0} = regs{12-0}; let Inst{12-0} = regs{12-0};
} }
▲ Show 20 Lines • Show All 226 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/ARM/clrm.txt

Show All 10 Lines
# CHECK: clrm {r12} @ encoding: [0x9f,0xe8,0x00,0x10] # CHECK: clrm {r12} @ encoding: [0x9f,0xe8,0x00,0x10]
[0x9f,0xe8,0x00,0x40] [0x9f,0xe8,0x00,0x40]
# CHECK: clrm {lr} @ encoding: [0x9f,0xe8,0x00,0x40] # CHECK: clrm {lr} @ encoding: [0x9f,0xe8,0x00,0x40]
[0x9f,0xe8,0x00,0x80] [0x9f,0xe8,0x00,0x80]
# CHECK: clrm {apsr} @ encoding: [0x9f,0xe8,0x00,0x80] # CHECK: clrm {apsr} @ encoding: [0x9f,0xe8,0x00,0x80]
[0x04,0xbf]
[0x9f,0xe8,0x0f,0x00]
# CHECK: itt eq
# CHECK: clrmeq {r0, r1, r2, r3}
[0x9f,0xe8,0x00,0x00] [0x9f,0xe8,0x00,0x00]
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding # ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding