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[X86][SSE] Added general integer shuffle matching for MOVQ instruction

Authored by RKSimon on Jan 29 2015, 8:48 AM.



This patch adds general shuffle pattern matching for the MOVQ zero-extend instruction (copy lower 64bits, zero upper) for all 128-bit integer vectors, it is added as a fallback test in lowerVectorShuffleAsZeroOrAnyExtend.

Regarding the issues in the tests - combine-or.ll is fixed in conjunction with D6649 (which reduces it to a shift + movq) and the superfluous movq after the pshufb in vector-shuffle-128-v16.ll are resolved once x86-experimental-vector-shuffle-legality is enabled.

This is a follow-up to D7228 which adds shuffle decodes / assembly comments for the movq comments - if that ticket gets approved I can update this patch's tests to include the comments.

Note I have other patterns to add to lowerVectorShuffleAsZeroOrAnyExtend shortly.

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RKSimon updated this revision to Diff 18967.Jan 29 2015, 8:48 AM
RKSimon retitled this revision from to [X86][SSE] Added general integer shuffle matching for MOVQ instruction.
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RKSimon updated this revision to Diff 19092.Jan 31 2015, 8:17 AM

Updated with assembly comments now that D7228 has been committed.

Also added additional tests against 4i32 and 8i16 vectors.

chandlerc accepted this revision.Feb 3 2015, 10:20 AM
chandlerc edited edge metadata.

Minor comments. Good to go with these.


I would call this "CanZExtLowHalf", and document that it returns the input whose low half can be zext-ed.

Also, no need to use an explicit return in the lambda, it should be deduced.


I would call the variable 'V'. It isn't a MOVQ (yet).

This revision is now accepted and ready to land.Feb 3 2015, 10:20 AM
RKSimon closed this revision.Feb 3 2015, 12:14 PM

Thanks Chandler, committed with your changes.