[mlir][spirv] Add lowering for std.fpext, std.fptrunc, std.sitofp.

[mravishankar]

Thanks!

[antiagainst]

Thanks!

mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.td

34

Super nit: insert an empty line between BinaryOpPatterns and UnaryOpPatterns?

[denis13]

Thanks for review, updated!

[antiagainst]

Oops, I'm sorry it seems I messed up with the author of the commit when landing this commit... Truly sorry about this...

[antiagainst]

The review-on-Phabricator-and-then-use-CLI-git-amend-and-then-git-commit workflow is really cumbersome and error-prone... I wish we can have GitHub pull requests.

[antiagainst]

Fixed by reverting via https://github.com/llvm/llvm-project/commit/dab2921f77099534ff19fead9a79fbff312feabf and re-landed as https://github.com/llvm/llvm-project/commit/eac01f63a6c99d6ffd03b7b7c88cf8e28d364e5c.

mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.td

 
 include "mlir/Dialect/StandardOps/Ops.td"
 include "mlir/Dialect/SPIRV/SPIRVOps.td"
 
 class BinaryOpPattern<Type type, Op src, Op tgt> :
       Pat<(src SPV_ScalarOrVectorOf<type>:$l, SPV_ScalarOrVectorOf<type>:$r),
           (tgt $l, $r)>;
 
+class UnaryOpPattern<Type type, Op src, Op tgt> :
+      Pat<(src type:$input),
+          (tgt $input)>;
+
 def : BinaryOpPattern<SPV_Bool, AndOp, SPV_LogicalAndOp>;
 def : BinaryOpPattern<SPV_Bool, OrOp, SPV_LogicalOrOp>;
 def : BinaryOpPattern<SPV_Float, AddFOp, SPV_FAddOp>;
 def : BinaryOpPattern<SPV_Float, DivFOp, SPV_FDivOp>;
 def : BinaryOpPattern<SPV_Float, MulFOp, SPV_FMulOp>;
 def : BinaryOpPattern<SPV_Float, RemFOp, SPV_FRemOp>;
 def : BinaryOpPattern<SPV_Float, SubFOp, SPV_FSubOp>;
 
+def : UnaryOpPattern<SPV_Integer, SIToFPOp, SPV_ConvertSToFOp>;
+def : UnaryOpPattern<SPV_Float, FPExtOp, SPV_FConvertOp>;
+def : UnaryOpPattern<SPV_Float, FPTruncOp, SPV_FConvertOp>;
+
 // Constant Op
 // TODO(ravishankarm): Handle lowering other constant types.
 def : Pat<(ConstantOp:$result $valueAttr),
           (SPV_ConstantOp $valueAttr),
           [(SPV_ScalarOrVector $result)]>;
 
 #endif // MLIR_CONVERSION_STANDARDTOSPIRV_TD

mlir/test/Conversion/StandardToSPIRV/std-to-spirv.mlir

func @logical_vector_fail(%arg0 : vector<4xi32>, %arg1 : vector<4xi32>) {
   // CHECK-NOT: spv.LogicalAnd
   %0 = and %arg0, %arg1 : vector<4xi32>
   // CHECK-NOT: spv.LogicalOr
   %1 = or %arg0, %arg1 : vector<4xi32>
   return
 }
 
 //===----------------------------------------------------------------------===//
+// std.fpext
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @fpext
+func @fpext(%arg0 : f32) {
+  // CHECK: spv.FConvert
+  %0 = std.fpext %arg0 : f32 to f64
+  return
+}
+
+//===----------------------------------------------------------------------===//
+// std.fptrunc
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @fptrunc
+func @fptrunc(%arg0 : f64) {
+  // CHECK: spv.FConvert
+  %0 = std.fptrunc %arg0 : f64 to f32
+  return
+}
+
+//===----------------------------------------------------------------------===//
 // std.select
 //===----------------------------------------------------------------------===//
 
 // CHECK-LABEL: @select
 func @select(%arg0 : i32, %arg1 : i32) {
   %0 = cmpi "sle", %arg0, %arg1 : i32
   // CHECK: spv.Select
   %1 = select %0, %arg0, %arg1 : i32
   return
 }
+
+//===----------------------------------------------------------------------===//
+// std.sitofp
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @sitofp
+func @sitofp(%arg0 : i32) {
+  // CHECK: spv.ConvertSToF
+  %0 = std.sitofp %arg0 : i32 to f32
+  return
+}