This is an archive of the discontinued LLVM Phabricator instance.

[llvm][MIRVRegNamerUtils] Add support for hashing MachineOperand FrameIndices.
ClosedPublic

Authored by plotfi on Dec 16 2019, 5:07 PM.

Details

Summary

This patch makes it so that cases where multiple instructions that differ only in their frame-index MachineOperand values no longer collide. For instance:

%1:_(p0) = G_FRAME_INDEX %stack.0
%2:_(p0) = G_FRAME_INDEX %stack.1
%3:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _
%4:gr32 = MOV32rm %fixed-stack.1, 1, _, 0,

Prior to this patch the first two instructions would collide together. Also, the last two instructions would also collide. Now they will no longer collide.

Diff Detail

Event Timeline

plotfi created this revision.Dec 16 2019, 5:07 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 16 2019, 5:07 PM
This revision is now accepted and ready to land.Dec 18 2019, 10:44 PM
This revision was automatically updated to reflect the committed changes.