[ELF][PPC64] Fix IPLT entry in .glink

lld/ELF/Arch/PPC64.cpp

void PPC64::writePltHeader(uint8_t *buf) const {
   // instruction  to the first entry in the GotPlt section.
   int64_t gotPltOffset = in.gotPlt->getVA() - (in.plt->getVA() + 8);
   write64(buf + 52, gotPltOffset);
 }
 
 void PPC64::writePlt(uint8_t *buf, uint64_t gotPltEntryAddr,
                      uint64_t pltEntryAddr, int32_t index,
                      unsigned relOff) const {
+  if (index < 0) {
+    int64_t offset = gotPltEntryAddr - getPPC64TocBase();
+    uint16_t offHa = (offset + 0x8000) >> 16;
+    uint16_t offLo = offset & 0xffff;
+
+    write32(buf + 0, 0x3d820000 | offHa); // addis r12, r2, OffHa
+    write32(buf + 4, 0xe98c0000 | offLo); // ld    r12, OffLo(r12)
+    write32(buf + 8, 0x7d8903a6);         // mtctr r12
+    write32(buf + 12, 0x4e800420);        // bctr
+  } else {
     int32_t offset = pltHeaderSize + index * pltEntrySize;
     // bl __glink_PLTresolve
     write32(buf, 0x48000000 | ((-offset) & 0x03FFFFFc));
   }
+}
 
 static std::pair<RelType, uint64_t> toAddr16Rel(RelType type, uint64_t val) {
   // Relocations relative to the toc-base need to be adjusted by the Toc offset.
   uint64_t tocBiasedVal = val - ppc64TocOffset;
   // Relocations relative to dtv[dtpmod] need to be adjusted by the DTP offset.
   uint64_t dtpBiasedVal = val - dynamicThreadPointerOffset;
 
   switch (type) {

lld/ELF/SyntheticSections.cpp

void PltSection::writeTo(uint8_t *buf) {
   // The IPlt is immediately after the Plt, account for this in relOff
   size_t pltOff = isIplt ? in.plt->getSize() : 0;
 
   for (size_t i = 0, e = entries.size(); i != e; ++i) {
     const Symbol *b = entries[i];
     unsigned relOff = relSec->entsize * i + pltOff;
     uint64_t got = b->getGotPltVA();
     uint64_t plt = this->getVA() + off;
-    target->writePlt(buf + off, got, plt, b->pltIndex, relOff);
+    int index = isIplt ? -1 : (int)b->pltIndex;
+    target->writePlt(buf + off, got, plt, index, relOff);
     off += target->pltEntrySize;
   }
 }
 
 template <class ELFT> void PltSection::addEntry(Symbol &sym) {
   sym.pltIndex = entries.size();
   entries.push_back(&sym);
 }
 
 size_t PltSection::getSize() const {
+  if (config->emachine == EM_PPC64 && isIplt)
+    return entries.size() * 16;
   return headerSize + entries.size() * target->pltEntrySize;
 }
 
 // Some architectures such as additional symbols in the PLT section. For
 // example ARM uses mapping symbols to aid disassembly
 void PltSection::addSymbols() {
   // The PLT may have symbols defined for the Header, the IPLT has no header
   if (!isIplt)