Change representation of member function pointers for MIPS targets

[zoran.jovanovic]

Summary

Member function pointer is represented with 2 words: <ptr, adj>
Currently, last significant bit of 'ptr' is used for marking virtual functions.
This can not be used for microMIPS and mips16 because odd addresses are valid for these platforms.
Patch introduces new TargetCXXABI - GenericMips. Only difference compered to GenericItanium (used for MIPS until now) is that it sets UseARMMethodPtrABI to true.
In order to be able to link with code for other MIPS targets and with code generated with gcc this should be used for all MIPS targets.

[dsanders]

I'm not particularly knowledgeable about C++ ABI's but I have compared the gcc and clang output and I agree that this change makes the representation the same as gcc's. I tested MIPS32r2 and microMIPS. On that basis, LGTM apart from TargetCXXABI::tryParse() as noted below.

lib/Basic/TargetInfo.cpp

658

Shouldn't "arm" be "mips" here?

[atanasyan]

LGTM

include/clang/Basic/TargetCXXABI.h

enum Kind {
     /// The generic AArch64 ABI is also a modified version of the Itanium ABI,
     /// but it has fewer divergences than the 32-bit ARM ABI.
     ///
     /// The relevant changes from the generic ABI in this case are:
     ///   - representation of member function pointers adjusted as in ARM.
     ///   - guard variables  are smaller.
     GenericAArch64,
 
+    /// The generic Mips ABI is a modified version of the Itanium ABI.
+    ///
+    /// At the moment, only change from the generic ABI in this case is:
+    ///   - representation of member function pointers adjusted as in ARM.
+    GenericMIPS,
+
     /// The Microsoft ABI is the ABI used by Microsoft Visual Studio (and
     /// compatible compilers).
     ///
     /// FIXME: should this be split into Win32 and Win64 variants?
     ///
     /// Only scattered and incomplete official documentation exists.
     Microsoft
   };
public:
   /// \brief Does this ABI generally fall into the Itanium family of ABIs?
   bool isItaniumFamily() const {
     switch (getKind()) {
     case GenericAArch64:
     case GenericItanium:
     case GenericARM:
     case iOS:
     case iOS64:
+    case GenericMIPS:
       return true;
 
     case Microsoft:
       return false;
     }
     llvm_unreachable("bad ABI kind");
   }
 
   /// \brief Is this ABI an MSVC-compatible ABI?
   bool isMicrosoft() const {
     switch (getKind()) {
     case GenericAArch64:
     case GenericItanium:
     case GenericARM:
     case iOS:
     case iOS64:
+    case GenericMIPS:
       return false;
 
     case Microsoft:
       return true;
     }
     llvm_unreachable("bad ABI kind");
   }
 
bool canKeyFunctionBeInline() const {
     case GenericARM:
     case iOS64:
       return false;
 
     case GenericAArch64:
     case GenericItanium:
     case iOS:   // old iOS compilers did not follow this rule
     case Microsoft:
+    case GenericMIPS:
       return true;
     }
     llvm_unreachable("bad ABI kind");
   }
 
   /// When is record layout allowed to allocate objects in the tail
   /// padding of a base class?
   ///
TailPaddingUseRules getTailPaddingUseRules() const {
     switch (getKind()) {
     // To preserve binary compatibility, the generic Itanium ABI has
     // permanently locked the definition of POD to the rules of C++ TR1,
     // and that trickles down to all the derived ABIs.
     case GenericItanium:
     case GenericAArch64:
     case GenericARM:
     case iOS:
+    case GenericMIPS:
       return UseTailPaddingUnlessPOD03;
 
     // iOS on ARM64 uses the C++11 POD rules.  It does not honor the
     // Itanium exception about classes with over-large bitfields.
     case iOS64:
       return UseTailPaddingUnlessPOD11;
 
     // MSVC always allocates fields in the tail-padding of a base class

lib/AST/ASTContext.cpp

 CXXABI *ASTContext::createCXXABI(const TargetInfo &T) {
   if (!LangOpts.CPlusPlus) return nullptr;
 
   switch (T.getCXXABI().getKind()) {
   case TargetCXXABI::GenericARM: // Same as Itanium at this level
   case TargetCXXABI::iOS:
   case TargetCXXABI::iOS64:
   case TargetCXXABI::GenericAArch64:
+  case TargetCXXABI::GenericMIPS:
   case TargetCXXABI::GenericItanium:
     return CreateItaniumCXXABI(*this);
   case TargetCXXABI::Microsoft:
     return CreateMicrosoftCXXABI(*this);
   }
   llvm_unreachable("Invalid CXXABI type!");
 }
 
VTableContextBase *ASTContext::getVTableContext() {
   return VTContext.get();
 }
 
 MangleContext *ASTContext::createMangleContext() {
   switch (Target->getCXXABI().getKind()) {
   case TargetCXXABI::GenericAArch64:
   case TargetCXXABI::GenericItanium:
   case TargetCXXABI::GenericARM:
+  case TargetCXXABI::GenericMIPS:
   case TargetCXXABI::iOS:
   case TargetCXXABI::iOS64:
     return ItaniumMangleContext::create(*this, getDiagnostics());
   case TargetCXXABI::Microsoft:
     return MicrosoftMangleContext::create(*this, getDiagnostics());
   }
   llvm_unreachable("Unsupported ABI");
 }

lib/Basic/TargetInfo.cpp

 
 bool TargetCXXABI::tryParse(llvm::StringRef name) {
   const Kind unknown = static_cast<Kind>(-1);
   Kind kind = llvm::StringSwitch<Kind>(name)
     .Case("arm", GenericARM)
     .Case("ios", iOS)
     .Case("itanium", GenericItanium)
     .Case("microsoft", Microsoft)
+    .Case("arm", GenericMIPS)
     .Default(unknown);
   if (kind == unknown) return false;
 
   set(kind);
   return true;
 }

lib/Basic/Targets.cpp

protected:
   bool HasFP64;
   std::string ABI;
 
 public:
   MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
                      const std::string &CPUStr)
       : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
         IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
-        DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
+        DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
+    TheCXXABI.set(TargetCXXABI::GenericMIPS);
+  }
 
   bool isNaN2008Default() const {
     return CPU == "mips32r6" || CPU == "mips64r6";
   }
 
   bool isFP64Default() const {
     return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
   }

lib/CodeGen/CodeGenModule.cpp

 static const char AnnotationSection[] = "llvm.metadata";
 
 static CGCXXABI *createCXXABI(CodeGenModule &CGM) {
   switch (CGM.getTarget().getCXXABI().getKind()) {
   case TargetCXXABI::GenericAArch64:
   case TargetCXXABI::GenericARM:
   case TargetCXXABI::iOS:
   case TargetCXXABI::iOS64:
+  case TargetCXXABI::GenericMIPS:
   case TargetCXXABI::GenericItanium:
     return CreateItaniumCXXABI(CGM);
   case TargetCXXABI::Microsoft:
     return CreateMicrosoftCXXABI(CGM);
   }
 
   llvm_unreachable("invalid C++ ABI kind");
 }

lib/CodeGen/ItaniumCXXABI.cpp

CodeGen::CGCXXABI *CodeGen::CreateItaniumCXXABI(CodeGenModule &CGM) {
 
   // Note that AArch64 uses the generic ItaniumCXXABI class since it doesn't
   // include the other 32-bit ARM oddities: constructor/destructor return values
   // and array cookies.
   case TargetCXXABI::GenericAArch64:
     return new ItaniumCXXABI(CGM, /* UseARMMethodPtrABI = */ true,
                              /* UseARMGuardVarABI = */ true);
 
+  case TargetCXXABI::GenericMIPS:
+    return new ItaniumCXXABI(CGM, /* UseARMMethodPtrABI = */ true);
+
   case TargetCXXABI::GenericItanium:
     if (CGM.getContext().getTargetInfo().getTriple().getArch()
         == llvm::Triple::le32) {
       // For PNaCl, use ARM-style method pointers so that PNaCl code
       // does not assume anything about the alignment of function
       // pointers.
       return new ItaniumCXXABI(CGM, /* UseARMMethodPtrABI = */ true,
                                /* UseARMGuardVarABI = */ false);

test/CodeGenCXX/member-function-pointers.cpp

 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=x86_64-unknown-unknown | FileCheck -check-prefix CODE-LP64 %s
 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=i386-unknown-unknown | FileCheck -check-prefix CODE-LP32 %s
 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=x86_64-unknown-unknown | FileCheck -check-prefix GLOBAL-LP64 %s
 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=i386-unknown-unknown | FileCheck -check-prefix GLOBAL-LP32 %s
 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=armv7-unknown-unknown | FileCheck -check-prefix GLOBAL-ARM %s
 
 // PNaCl uses the same representation of method pointers as ARM.
 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=le32-unknown-nacl | FileCheck -check-prefix GLOBAL-ARM %s
+// MIPS uses the same representation of method pointers as ARM.
+// RUN: %clang_cc1 %s -emit-llvm -o - -triple=mips-unknown-linux-gnu | FileCheck -check-prefix GLOBAL-ARM %s
 
 struct A { int a; void f(); virtual void vf1(); virtual void vf2(); };
 struct B { int b; virtual void g(); };
 struct C : B, A { };
 
 void (A::*pa)();
 void (A::*volatile vpa)();
 void (B::*pb)();