Mips: Make test resistant to future changes

[arsenm]

Summary

This seems to have been relying on extra spills being inserted in
these blocks to increase the code size to trigger branch
relaxation. This broke when these spills were avoided. Add some asm to
pad the size of the blocks to make it not matter.

[atanasyan]

LGTM

[arsenm]

f9677c47573f7933dd6ea6fe3086fb58e159969a

llvm/test/CodeGen/Mips/branch-relaxation-with-hazard.ll

entry:
   store i32 0, i32* %retval, align 4
   store i32 %argc, i32* %argc.addr, align 4
   store i8** %argv, i8*** %argv.addr, align 4
   %0 = load i32, i32* %argc.addr, align 4
   %cmp = icmp sgt i32 %0, 1
   br i1 %cmp, label %if.then, label %if.end4
 
 if.then:
+  call void asm sideeffect ".space 10", "~{$1}"()
   %1 = load i32, i32* %argc.addr, align 4
   %cmp1 = icmp sgt i32 %1, 3
   br i1 %cmp1, label %if.then2, label %if.end
 
 if.then2:
+  call void asm sideeffect ".space 10", "~{$1}"()
   %call = call i32 bitcast (i32 (...)* @boo to i32 ()*)()
   store i32 %call, i32* %retval, align 4
   br label %return
 
 if.end:
   call void asm sideeffect ".space 4194228", "~{$1}"()
   %call3 = call i32 bitcast (i32 (...)* @foo to i32 ()*)()
   store i32 %call3, i32* %retval, align 4