[MIRVRegNamerUtils] Add additional hashing on MachineInstr flags.

[plotfi]

Summary

How does this idea sound? I'd also add the inline asm stuff, but I know that is not useful atm.

TODO: Will post test before any landing.

[aditya_nandakumar]

llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

99

I'd probably just do

if (unsigned Flag = MI.getFlags())
  MIOperands.push_back(Flag);

That should be equivalent to what you're doing above.
In fact, I'd just simplify it to

MIOperands.push_back(MI.getFlags());

with 0 (no flags) being also valid enough to contribute to the hash.

[plotfi]

Adding test case.

[plotfi]

llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

99

ditto

llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

auto GetHashableMO = [this](const MachineOperand &MO) -> unsigned {
     // We could explicitly handle all the types of the MachineOperand,
     // here but we can just return a common number until we find a
     // compelling test case where this is bad. The only side effect here
     // is contributing to a hash collision but there's enough information
     // (Opcodes,other registers etc) that this will likely not be a problem.
     return 0;
   };
 
-  SmallVector<unsigned, 16> MIOperands = {MI.getOpcode()};
+  SmallVector<unsigned, 16> MIOperands = {MI.getOpcode(), MI.getFlags()};
   llvm::transform(MI.uses(), std::back_inserter(MIOperands), GetHashableMO);
 
   auto HashMI = hash_combine_range(MIOperands.begin(), MIOperands.end());
   return std::to_string(HashMI).substr(0, 5);
 }
 
 unsigned VRegRenamer::createVirtualRegister(unsigned VReg) {
   assert(Register::isVirtualRegister(VReg) && "Expected Virtual Registers");
if (Candidate.mayStore() || Candidate.isBranch())
       continue;
     if (!Candidate.getNumOperands())
       continue;
     // Look for instructions that define VRegs in operand 0.
     MachineOperand &MO = Candidate.getOperand(0);
     // Avoid non regs, instructions defining physical regs.
     if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
       continue;
     VRegs.push_back(
         NamedVReg(MO.getReg(), Prefix + getInstructionOpcodeHash(Candidate)));
   }
 
   return VRegs.size() ? doVRegRenaming(getVRegRenameMap(VRegs)) : false;
 }
 
 bool VRegRenamer::renameVRegs(MachineBasicBlock *MBB, unsigned BBNum) {
   CurrentBBNumber = BBNum;

llvm/test/CodeGen/MIR/X86/mircanon-flags.mir

+# RUN: llc -march=x86-64 -run-pass mir-canonicalizer -o - %s | FileCheck %s
+# The purpose of this test is to ensure that differing flags do in-fact cause
+# naming collisions with the new vreg renamers naming scheme.
+--- |
+  target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+  define void @baz() { unreachable }
+...
+---
+name:            baz
+body:             |
+  bb.0:
+
+    ; CHECK: %bb0_{{[0-9]+}}__1:fr32 = COPY $xmm0
+    ; CHECK: %bb0_{{[0-9]+}}__1:fr32 = nnan VMULSSrr
+    ; CHECK: %bb0_{{[0-9]+}}__1:fr32 = ninf VMULSSrr
+    ; CHECK: %bb0_{{[0-9]+}}__1:fr32 = nsz VMULSSrr
+    ; CHECK: %bb0_{{[0-9]+}}__1:fr32 = arcp VMULSSrr
+    ; CHECK: %bb0_{{[0-9]+}}__1:fr32 = contract VMULSSrr
+    ; CHECK: %bb0_{{[0-9]+}}__1:fr32 = afn VMULSSrr
+    ; CHECK: %bb0_{{[0-9]+}}__1:fr32 = reassoc VMULSSrr
+    ; CHECK: %bb0_{{[0-9]+}}__1:fr32 = nsz arcp contract
+    ; CHECK: %bb0_{{[0-9]+}}__1:fr32 = contract afn reassoc
+
+    %0:fr32 = COPY $xmm0
+    %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
+    %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
+    %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
+    %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
+    %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
+    %6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
+    %7:fr32 = reassoc VMULSSrr %6, %6, implicit $mxcsr
+    %8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
+    %9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
+    $xmm0 = COPY %9
+    RET 0, $xmm0
+
+...