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Differential D70124

[RISCV] Use addi rather than add x0
ClosedPublic

Authored by lenary on Nov 12 2019, 7:26 AM.

Details

Reviewers
luismarques
Commits
rG32d840d29179: [RISCV] Use addi rather than add x0
Summary

The RISC-V backend used to generate add <reg>, x0, <reg> in a few
instances. It seems most places no longer generate this sequence.

This is semantically equivalent to addi <reg>, <reg>, 0, but the
latter has the advantage of being noted to be the canonical instruction
to be used for moves (which microarchitectures can and should recognise
as such).

The changed testcases use instruction aliases - mv <reg>, <reg> is an
alias for addi <reg>, <reg>, 0.

Diff Detail

Event Timeline

lenary created this revision.Nov 12 2019, 7:26 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 12 2019, 7:26 AM
Herald added subscribers: llvm-commits, sameer.abuasal, pzheng and 25 others. · View Herald Transcript
Harbormaster completed remote builds in B40816: Diff 228893.Nov 12 2019, 7:31 AM
luismarques accepted this revision.Nov 12 2019, 7:53 AM

LGTM.

This revision is now accepted and ready to land.Nov 12 2019, 7:53 AM
Closed by commit rG32d840d29179: [RISCV] Use addi rather than add x0 (authored by lenary). · Explain WhyNov 14 2019, 10:52 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
6 lines
test/
CodeGen/
RISCV/
40 lines

Diff 229356

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

Show First 20 Lines • Show All 313 Lines • ▼ Show 20 Linesstatic void doMaskedAtomicBinOpExpansion(
// sc.w scratch, scratch, (alignedaddr) // sc.w scratch, scratch, (alignedaddr)
// bnez scratch, loop // bnez scratch, loop
BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg) BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
.addReg(AddrReg); .addReg(AddrReg);
switch (BinOp) { switch (BinOp) {
default: default:
llvm_unreachable("Unexpected AtomicRMW BinOp"); llvm_unreachable("Unexpected AtomicRMW BinOp");
case AtomicRMWInst::Xchg: case AtomicRMWInst::Xchg:
BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg) BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg)
.addReg(RISCV::X0) .addReg(IncrReg)
.addReg(IncrReg); .addImm(0);
break; break;
case AtomicRMWInst::Add: case AtomicRMWInst::Add:
BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg) BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg)
.addReg(DestReg) .addReg(DestReg)
.addReg(IncrReg); .addReg(IncrReg);
break; break;
case AtomicRMWInst::Sub: case AtomicRMWInst::Sub:
BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg) BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg)
▲ Show 20 Lines • Show All 384 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/atomic-rmw.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show All 24 Lines
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: mv a5, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w a5, a5, (a2) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB0_1 ; RV32IA-NEXT: bnez a5, .LBB0_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
Show All 14 Lines
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: mv a5, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w a5, a5, (a2) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB0_1 ; RV64IA-NEXT: bnez a5, .LBB0_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
Show All 18 Lines
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2) ; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: mv a5, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w a5, a5, (a2) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB1_1 ; RV32IA-NEXT: bnez a5, .LBB1_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
Show All 14 Lines
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2) ; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: mv a5, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w a5, a5, (a2) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB1_1 ; RV64IA-NEXT: bnez a5, .LBB1_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
Show All 18 Lines
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a2) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: mv a5, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB2_1 ; RV32IA-NEXT: bnez a5, .LBB2_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
Show All 14 Lines
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a2) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: mv a5, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB2_1 ; RV64IA-NEXT: bnez a5, .LBB2_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
Show All 18 Lines
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a2) ; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: mv a5, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB3_1 ; RV32IA-NEXT: bnez a5, .LBB3_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
Show All 14 Lines
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a2) ; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: mv a5, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB3_1 ; RV64IA-NEXT: bnez a5, .LBB3_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
Show All 18 Lines
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: addi a3, zero, 255 ; RV32IA-NEXT: addi a3, zero, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a2) ; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: mv a5, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB4_1 ; RV32IA-NEXT: bnez a5, .LBB4_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
Show All 14 Lines
; RV64IA-NEXT: slli a0, a0, 3 ; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255 ; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a2) ; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: mv a5, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB4_1 ; RV64IA-NEXT: bnez a5, .LBB4_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
▲ Show 20 Lines • Show All 4,689 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a2) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: mv a5, a1
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w a5, a5, (a2) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB55_1 ; RV32IA-NEXT: bnez a5, .LBB55_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
Show All 15 Lines
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a2) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: mv a5, a1
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w a5, a5, (a2) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB55_1 ; RV64IA-NEXT: bnez a5, .LBB55_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
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; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a2) ; RV32IA-NEXT: lr.w.aq a3, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: mv a5, a1
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w a5, a5, (a2) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB56_1 ; RV32IA-NEXT: bnez a5, .LBB56_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
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; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a2) ; RV64IA-NEXT: lr.w.aq a3, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: mv a5, a1
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w a5, a5, (a2) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB56_1 ; RV64IA-NEXT: bnez a5, .LBB56_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
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; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a2) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: mv a5, a1
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB57_1 ; RV32IA-NEXT: bnez a5, .LBB57_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
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; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a2) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: mv a5, a1
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB57_1 ; RV64IA-NEXT: bnez a5, .LBB57_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
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; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a2) ; RV32IA-NEXT: lr.w.aq a3, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: mv a5, a1
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.rl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB58_1 ; RV32IA-NEXT: bnez a5, .LBB58_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
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; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a2) ; RV64IA-NEXT: lr.w.aq a3, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: mv a5, a1
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.rl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB58_1 ; RV64IA-NEXT: bnez a5, .LBB58_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
Show All 19 Lines
; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a0, a0, 24
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a2) ; RV32IA-NEXT: lr.w.aqrl a3, (a2)
; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: mv a5, a1
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB59_1 ; RV32IA-NEXT: bnez a5, .LBB59_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
Show All 15 Lines
; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a2) ; RV64IA-NEXT: lr.w.aqrl a3, (a2)
; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: mv a5, a1
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB59_1 ; RV64IA-NEXT: bnez a5, .LBB59_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
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