[AArch64] Use callee calling convention for RegMask and return value

[scw]

Summary

When lowering calls and tail calls in AArch64, the register mask and
return value location depends on the calling convention of the callee.
F.getCallingConv(), however, is the caller CC. Correct it to the
callee CC from CallLoweringInfo.

Fixes PR43449

[paquette]

Nice! LGTM

[scw]

Thank you Jessica for the review. I don't have submit permission, could you do it for me? Thank you!

[paquette]

Sure! I just need to get my commit access transferred from SVN to GitHub and then I'll commit it for you.

(Or maybe @echristo can commit it?)

[echristo]

Done thusly:

To github.com:llvm/llvm-project.git

703c97be249..8d694a45ab6  master -> master

Pay attention to the bots as will I :)

[scw]

Submitted as llvmorg-10-init-9268-g8d694a45ab6

llvm/lib/Target/AArch64/AArch64CallLowering.cpp

bool AArch64CallLowering::lowerTailCall(
   MIB.add(Info.Callee);
 
   // Byte offset for the tail call. When we are sibcalling, this will always
   // be 0.
   MIB.addImm(0);
 
   // Tell the call which registers are clobbered.
   auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
-  const uint32_t *Mask = TRI->getCallPreservedMask(MF, F.getCallingConv());
+  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CalleeCC);
   if (MF.getSubtarget<AArch64Subtarget>().hasCustomCallingConv())
     TRI->UpdateCustomCallPreservedMask(MF, &Mask);
   MIB.addRegMask(Mask);
 
   if (TRI->isAnyArgRegReserved(MF))
     TRI->emitReservedArgRegCallError(MF);
 
   // FPDiff is the byte offset of the call's argument area from the callee's.
bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
   // uses of arg registers.
   unsigned Opc = getCallOpcode(F, Info.Callee.isReg(), false);
 
   auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
   MIB.add(Info.Callee);
 
   // Tell the call which registers are clobbered.
   auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
-  const uint32_t *Mask = TRI->getCallPreservedMask(MF, F.getCallingConv());
+  const uint32_t *Mask = TRI->getCallPreservedMask(MF, Info.CallConv);
   if (MF.getSubtarget<AArch64Subtarget>().hasCustomCallingConv())
     TRI->UpdateCustomCallPreservedMask(MF, &Mask);
   MIB.addRegMask(Mask);
 
   if (TRI->isAnyArgRegReserved(MF))
     TRI->emitReservedArgRegCallError(MF);
 
   // Do the actual argument marshalling.
MIB->getOperand(0).setReg(constrainOperandRegClass(
         MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
         *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
         0));
 
   // Finally we can copy the returned value back into its virtual-register. In
   // symmetry with the arugments, the physical register must be an
   // implicit-define of the call instruction.
   if (!Info.OrigRet.Ty->isVoidTy()) {
-    CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
+    CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv);
     CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);
     if (!handleAssignments(MIRBuilder, InArgs, Handler))
       return false;
   }
 
   if (Info.SwiftErrorVReg) {
     MIB.addDef(AArch64::X21, RegState::Implicit);
     MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

; CHECK: G_ADD [[ARG]], [[C1]]
   ret i32 %res
 }
 
 declare ghccc float @different_call_conv_target(float %x)
 define float @test_different_call_conv_target(float %x) {
 ; CHECK-LABEL: name: test_different_call_conv
 ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $s0
 ; CHECK: $s8 = COPY [[X]]
-; CHECK: BL @different_call_conv_target, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s8, implicit-def $s0
+; CHECK: BL @different_call_conv_target, csr_aarch64_noregs, implicit-def $lr, implicit $sp, implicit $s8, implicit-def $s0
   %res = call ghccc float @different_call_conv_target(float %x)
   ret float %res
 }
 
 define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) {
 ; CHECK-LABEL: name: test_shufflevector_s32_v2s32
 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $w0
 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF

llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll

 
 ; Unsupported calling convention for tail calls. Make sure we never tail call
 ; it.
 declare ghccc void @bad_call_conv_fn()
 define void @test_bad_call_conv() {
   ; COMMON-LABEL: name: test_bad_call_conv
   ; COMMON: bb.1 (%ir-block.0):
   ; COMMON:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
-  ; COMMON:   BL @bad_call_conv_fn, csr_aarch64_aapcs, implicit-def $lr, implicit $sp
+  ; COMMON:   BL @bad_call_conv_fn, csr_aarch64_noregs, implicit-def $lr, implicit $sp
   ; COMMON:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; COMMON:   RET_ReallyLR
   tail call ghccc void @bad_call_conv_fn()
   ret void
 }
 
 ; Shouldn't tail call when the caller has byval arguments.
 define void @test_byval(i8* byval %ptr) {

llvm/test/CodeGen/AArch64/arm64-preserve-most.ll

+; RUN: llc -O0 --march=aarch64 -verify-machineinstrs --filetype=asm %s -o - 2>&1 | FileCheck %s
+; RUN: llc -O1 --march=aarch64 -verify-machineinstrs --filetype=asm %s -o - 2>&1 | FileCheck %s
+; RUN: llc -O2 --march=aarch64 -verify-machineinstrs --filetype=asm %s -o - 2>&1 | FileCheck %s
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+declare void @normal_cc()
+
+; Caller: preserve_mostcc; callee: normalcc. All normally callee saved registers
+; (x9 ~ x15) need to be spilled. Since most of them will be spilled in pairs
+; in reverse order, we only check the odd number ones since the same line of
+; assembly cannot be matched twice.
+; CHECK-LABEL: preserve_most
+; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x9(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
+; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x11(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
+; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x13(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
+; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x15(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
+define preserve_mostcc void @preserve_most() {
+  call void @normal_cc()
+  ret void
+}
+
+; Caller: normalcc; callee: preserve_mostcc. x9 does not need to be spilled.
+; The same holds for x10 through x15, but we only check x9.
+; CHECK-LABEL: normal_cc_caller
+; CHECK-NOT: stp {{x[0-9]+}}, x9, [sp, #{{[-0-9]+}}]
+; CHECK-NOT: stp x9, {{x[0-9]+}}, [sp, #{{[-0-9]+}}]
+; CHECK-NOT: str x9, [sp, {{#[-0-9]+}}]!
+define dso_local void @normal_cc_caller() {
+entry:
+  %v = alloca i32, align 4
+  call void asm sideeffect "mov x9, $0", "N,~{x9}"(i32 48879) #2
+  call preserve_mostcc void @preserve_most()
+  %0 = load i32, i32* %v, align 4
+  %1 = call i32 asm sideeffect "mov ${0:w}, w9", "=r,r"(i32 %0) #2
+  store i32 %1, i32* %v, align 4
+  ret void
+}