[AMDGPU] Add handling of 160 bit registers in analyzeResourceUsage

[rampitec]

Summary

This was omitted. Also SReg_96Reg missed IsSGPR assignment.

[arsenm]

Needs testcase

[rampitec]

In D69919#1736276, @arsenm wrote:

Needs testcase

Do we have an existing testcase for this part?

[arsenm]

In D69919#1736310, @rampitec wrote:

In D69919#1736276, @arsenm wrote:

Needs testcase

Do we have an existing testcase for this part?

101abd219b3dc77fb531e569e4b6bd86ed48b5c1 fixed the same problem for SGPR96 and tested this with inline asm

[rampitec]

Added test.

[arsenm]

LGTM

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

for (const MachineInstr &MI : MBB) {
         } else if (AMDGPU::AReg_64RegClass.contains(Reg)) {
           IsSGPR = false;
           IsAGPR = true;
           Width = 2;
         } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
           IsSGPR = false;
           Width = 3;
         } else if (AMDGPU::SReg_96RegClass.contains(Reg)) {
+          IsSGPR = true;
           Width = 3;
         } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
           assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
             "trap handler registers should not be used");
           IsSGPR = true;
           Width = 4;
         } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
           IsSGPR = false;
           Width = 4;
         } else if (AMDGPU::AReg_128RegClass.contains(Reg)) {
           IsSGPR = false;
           IsAGPR = true;
           Width = 4;
+        } else if (AMDGPU::VReg_160RegClass.contains(Reg)) {
+          IsSGPR = false;
+          Width = 5;
+        } else if (AMDGPU::SReg_160RegClass.contains(Reg)) {
+          IsSGPR = true;
+          Width = 5;
         } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
           assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
             "trap handler registers should not be used");
           IsSGPR = true;
           Width = 8;
         } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
           IsSGPR = false;
           Width = 8;

llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll

 ; GCN: NumVgprs: 24
 define amdgpu_kernel void @count_use_sgpr96_external_call()  {
 entry:
   tail call void asm sideeffect "; sgpr96 $0", "s"(<3 x i32> <i32 10, i32 11, i32 12>) #1
   call void @external()
   ret void
 }
 
+; Make sure there's no assert when a sgpr160 is used.
+; GCN-LABEL: {{^}}count_use_sgpr160_external_call
+; GCN: ; sgpr160 s[{{[0-9]+}}:{{[0-9]+}}]
+; CI: NumSgprs: 48
+; VI-NOBUG: NumSgprs: 48
+; VI-BUG: NumSgprs: 96
+; GCN: NumVgprs: 24
+define amdgpu_kernel void @count_use_sgpr160_external_call()  {
+entry:
+  tail call void asm sideeffect "; sgpr160 $0", "s"(<5 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14>) #1
+  call void @external()
+  ret void
+}
+
+; Make sure there's no assert when a vgpr160 is used.
+; GCN-LABEL: {{^}}count_use_vgpr160_external_call
+; GCN: ; vgpr160 v[{{[0-9]+}}:{{[0-9]+}}]
+; CI: NumSgprs: 48
+; VI-NOBUG: NumSgprs: 48
+; VI-BUG: NumSgprs: 96
+; GCN: NumVgprs: 24
+define amdgpu_kernel void @count_use_vgpr160_external_call()  {
+entry:
+  tail call void asm sideeffect "; vgpr160 $0", "v"(<5 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14>) #1
+  call void @external()
+  ret void
+}
+
 attributes #0 = { nounwind noinline norecurse }
 attributes #1 = { nounwind noinline norecurse }
 attributes #2 = { nounwind noinline }