AMDGPU: Don't fold S_NOPs with implicit operands

[rampitec]

LGTM

[arsenm]

edca9ac0de3a5c10a21ef0c725501ea35791006a

llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp

for (I = MBB.begin(); I != MBB.end(); I = Next) {
       // Combine adjacent s_nops to use the immediate operand encoding how long
       // to wait.
       //
       // s_nop N
       // s_nop M
       //  =>
       // s_nop (N + M)
       if (MI.getOpcode() == AMDGPU::S_NOP &&
+          MI.getNumOperands() == 1 && // Don't merge with implicit operands
           Next != MBB.end() &&
-          (*Next).getOpcode() == AMDGPU::S_NOP) {
+          (*Next).getOpcode() == AMDGPU::S_NOP &&
+          (*Next).getNumOperands() == 1) {
 
         MachineInstr &NextMI = *Next;
         // The instruction encodes the amount to wait with an offset of 1,
         // i.e. 0 is wait 1 cycle. Convert both to cycles and then convert back
         // after adding.
         uint8_t Nop0 = MI.getOperand(0).getImm() + 1;
         uint8_t Nop1 = NextMI.getOperand(0).getImm() + 1;
 

llvm/test/CodeGen/AMDGPU/nop-fold.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -run-pass=si-shrink-instructions %s -o - | FileCheck %s
+
+---
+
+name:            merge_2_nop
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: merge_2_nop
+    ; CHECK: S_NOP 1
+    S_NOP 0
+    S_NOP 0
+
+...
+
+---
+
+name:            merge_3_nop
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: merge_3_nop
+    ; CHECK: S_NOP 2
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+
+
+...
+
+---
+
+name:            merge_7_nop
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: merge_7_nop
+    ; CHECK: S_NOP 6
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+
+...
+
+---
+
+name:            merge_8_nop
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: merge_8_nop
+    ; CHECK: S_NOP 7
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+
+...
+---
+
+name:            merge_9_nop
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: merge_9_nop
+    ; CHECK: S_NOP 7
+    ; CHECK: S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+
+...
+
+---
+
+name:            no_merge_impdef0
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: no_merge_impdef0
+    ; CHECK: S_NOP 0, implicit-def $sgpr0
+    ; CHECK: S_NOP 0
+    S_NOP 0, implicit-def $sgpr0
+    S_NOP 0
+
+...
+
+---
+
+name:            no_merge_impdef1
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: no_merge_impdef1
+    ; CHECK: S_NOP 0
+    ; CHECK: S_NOP 0, implicit-def $sgpr0
+    S_NOP 0
+    S_NOP 0, implicit-def $sgpr0
+
+...
+
+---
+
+name:            no_merge_impdef_both
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: no_merge_impdef_both
+    ; CHECK: S_NOP 0
+    ; CHECK: S_NOP 0, implicit-def $sgpr0
+    S_NOP 0
+    S_NOP 0, implicit-def $sgpr0
+
+...