[ARM64] Cleanup and speedup NativeRegisterContextLinux_arm64

[omjavaid]

Summary

This patch simplifies register accesses in NativeRegisterContextLinux_arm64 and also adds some bare minimum caching to avoid multiple calls to ptrace during a stop.

Linux ptrace returns data in the form of structures containing GPR/FPR data. This means that one single call is enough to read all GPRs or FPRs. We do that once per stop and keep reading from or writing to the buffer that we have in NativeRegisterContextLinux_arm64 class. Before a resume or detach we write all buffers back.

This is tested on aarch64 thunder x1 with Ubuntu 18.04. Also tested regressions on x86_64.

[labath]

The idea seems nice, however I am wondering, if it is not going a bit too far. In not sure of the exact situation on arm64, but in general, there are registers which only accept some bit patterns. What exactly does ptrace do in this situation? Postponing the write until we resume/detach means we lose the opportunity to report any errors that would result from the ptrace call.

What's the exact case you're optimising for? Would it be enough to just cache the reads, but then as soon as we write something, we immediately call ptrace to ensure that the value was written successfully? It sounds like this could be enough as the majority of the operations should be reads...

source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

153–154 ↗

(On Diff #226214)

Please move these next to the members they are guarding.

[omjavaid]

We ll be dealing with Linux user mode and mostly aarch64 data registers except for cpsr, fpsr and fpcr. I think we should be fine but let me confirm this again from documentation.

Further more, motivation behind these changes is SVE register set which may exchange high volume of data due to large register sizes.

source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

153–154 ↗

(On Diff #226214)

Alright.

[labath]

In D69371#1721077, @omjavaid wrote:

We ll be dealing with Linux user mode and mostly aarch64 data registers except for cpsr, fpsr and fpcr. I think we should be fine but let me confirm this again from documentation.

Right, but you're creating a general interface for all architectures, not just several aarch64 registers. Even if they don't make use of that facility now, it would be good to make sure they can do that in the future.

For instance, on x86, the kernel may decide to reject https://github.com/torvalds/linux/blob/master/arch/x86/kernel/ptrace.c#L187 some values of some registers, and silently ignore some bits in others https://github.com/torvalds/linux/blob/master/arch/x86/kernel/ptrace.c#L349. That's why I think it would be better to commit changes to memory automatically/immediately, and minimize the chances that subsequent "read" operations will return data which does not reflect the actual values held by the OS.

[omjavaid]

Sorry for late response on this. I got side tracked into other issues and wanted performance testing before writing an update.

I agree with @labath about making caching for limited to reads only and register writes are written all the way in latest update.

Also according to performance tests these changes show no significant improvement on real hardware but if underlying hardware is a simulator like QEMU some improvement does occur. This is the main reason I am keeping these changes intact for register reads but have removed for register writes.

I have tested this patch on Ubuntu Bionic running on QEMU and Thunder X1 arm64 server.

LGTM?

[labath]

Thanks. I now agree with this change in principle, but I don't think its ready for an LGTM yet.

The main thing I'd like to discuss is this InvalidateAllRegisters function. I think we should come up with a story of when is this function expected to be called, and document it somewhere. Right now, the placement of call sites seems pretty random. For instance, it's not clear to me why one would need to call it in NativeProcessLinux::SetupSoftwareSingleStepping.

The reason we want to call this function is because the values that the kernel holds for this thread have (potentially) changed, and so we want to ensure we don't hold stale values. The way I see it, the values can change when:
a) we do a "register write" operation. It looks like you have this part covered, and the invalidation happens pretty close to the actual "write" syscall
b) when the thread gets a chance to run. I think this what the other InvalidateAllRegisters are trying to cover, but it's hard to tell because they are very far from the place where the actual thread gets resumed. In particular, the call in NativeProcessLinux::Resume seems troublesome, as it will call NativeThreadLinux::Resume *after* it "invalidates" the caches. However, NativeProcessLinux::Resume is responsible for setting the watchpoints, and this involves register read/writes, which may end up re-populating some caches. I guess that doesn't matter on arm because of how watchpoints are set, but I think it would make it easier to reason about these things if the invalidation happened right before we resume the thread, or immediately after it stops.

lldb/include/lldb/Host/common/NativeRegisterContext.h

112–113 ↗

(On Diff #231408)

Maybe this could be a method on NativeRegisterContextLinux. We can always later lift it to the main class if we find a reason to do that...

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

278–281

There's nothing happening after this if block, so you could write this so that it always returns (return WriteGPR()), and then drop the "else" from the next condition.

307–308

I guess this isn't needed, since Write[FG]PR already handle invalidation on their own?

878

Please change this to an early return (as well as the ReadGPR above).

[omjavaid]

Hi

I have updated this patch after incorporating previous suggestions like moving InvalidateAllRegisters declaration to NativeRegisterContextLinux and also relocated calls to InvalidateAllRegisters from NativeProcessLinux to NativeThreadLinux. We now call InvalidateAllRegisters just before we resume or single step via ptrace. Other than that on any register write register will be be invalidated by WriteGPR and WriteFPR as was happening previously. We dont really need a invalidate on detach because thread wont exist after that so I have removed it InvalidateAllRegisters which was being called at detach.

Also testing for GPR or FPR validity now happens outside WriteGPR and WriteFPR.

Thoughts?

[labath]

I think this looks good now. Thanks for your patience.

[labath]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux.h

32

no semicolon here

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux.h

public:
   // This function is implemented in the NativeRegisterContextLinux_* subclasses
   // to create a new instance of the host specific NativeRegisterContextLinux.
   // The implementations can't collide as only one NativeRegisterContextLinux_*
   // variant should be compiled into the final executable.
   static std::unique_ptr<NativeRegisterContextLinux>
   CreateHostNativeRegisterContextLinux(const ArchSpec &target_arch,
                                        NativeThreadProtocol &native_thread);
 
+  // Invalidates cached values in register context data structures
+  virtual void InvalidateAllRegisters(){};
+
 protected:
   lldb::ByteOrder GetByteOrder() const;
 
   virtual Status ReadRegisterRaw(uint32_t reg_index, RegisterValue &reg_value);
 
   virtual Status WriteRegisterRaw(uint32_t reg_index,
                                   const RegisterValue &reg_value);
 

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

public:
 
   Status WriteRegister(const RegisterInfo *reg_info,
                        const RegisterValue &reg_value) override;
 
   Status ReadAllRegisterValues(lldb::DataBufferSP &data_sp) override;
 
   Status WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override;
 
+  void InvalidateAllRegisters() override;
+
   // Hardware breakpoints/watchpoint management functions
 
   uint32_t NumSupportedHardwareBreakpoints() override;
 
   uint32_t SetHardwareBreakpoint(lldb::addr_t addr, size_t size) override;
 
   bool ClearHardwareBreakpoint(uint32_t hw_idx) override;
 
public:
   uint32_t GetWatchpointSize(uint32_t wp_index);
 
   bool WatchpointIsEnabled(uint32_t wp_index);
 
   // Debug register type select
   enum DREGType { eDREGTypeWATCH = 0, eDREGTypeBREAK };
 
 protected:
-  Status DoReadRegisterValue(uint32_t offset, const char *reg_name,
-                             uint32_t size, RegisterValue &value) override;
-
-  Status DoWriteRegisterValue(uint32_t offset, const char *reg_name,
-                              const RegisterValue &value) override;
 
   Status ReadGPR() override;
 
   Status WriteGPR() override;
 
   Status ReadFPR() override;
 
   Status WriteFPR() override;
private:
 
   // based on RegisterContextDarwin_arm64.h
   struct FPU {
     VReg v[32];
     uint32_t fpsr;
     uint32_t fpcr;
   };
 
-  uint64_t m_gpr_arm64[k_num_gpr_registers_arm64]; // 64-bit general purpose
-                                                   // registers.
+  struct GPR {
+    uint64_t x[31];
+    uint64_t sp;
+    uint64_t pc;
+    uint64_t pstate;
+  };
+
+  bool m_gpr_is_valid;
+  bool m_fpu_is_valid;
+
+  GPR m_gpr_arm64; // 64-bit general purpose registers.
   RegInfo m_reg_info;
   FPU m_fpr; // floating-point registers including extended register sets.
 
   // Debug register info for hardware breakpoints and watchpoints management.
   struct DREG {
     lldb::addr_t address;  // Breakpoint/watchpoint address value.
     lldb::addr_t hit_addr; // Address at which last watchpoint trigger exception
                            // occurred.

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64(
   ::memset(&m_gpr_arm64, 0, sizeof(m_gpr_arm64));
   ::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs));
   ::memset(&m_hbr_regs, 0, sizeof(m_hbr_regs));
 
   // 16 is just a maximum value, query hardware for actual watchpoint count
   m_max_hwp_supported = 16;
   m_max_hbp_supported = 16;
   m_refresh_hwdebug_info = true;
+
+  m_gpr_is_valid = false;
+  m_fpu_is_valid = false;
 }
 
 uint32_t NativeRegisterContextLinux_arm64::GetRegisterSetCount() const {
   return k_num_register_sets;
 }
 
 const RegisterSet *
 NativeRegisterContextLinux_arm64::GetRegisterSet(uint32_t set_index) const {
NativeRegisterContextLinux_arm64::ReadRegister(const RegisterInfo *reg_info,
 
   if (!reg_info) {
     error.SetErrorString("reg_info NULL");
     return error;
   }
 
   const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
 
-  if (IsFPR(reg)) {
-    error = ReadFPR();
+  if (reg == LLDB_INVALID_REGNUM)
+    return Status("no lldb regnum for %s", reg_info && reg_info->name
+                                               ? reg_info->name
+                                               : "<unknown register>");
+
+  uint8_t *src;
+  uint32_t offset;
+
+  if (IsGPR(reg)) {
+    if (!m_gpr_is_valid) {
+      error = ReadGPR();
       if (error.Fail())
         return error;
-  } else {
-    uint32_t full_reg = reg;
-    bool is_subreg = reg_info->invalidate_regs &&
-                     (reg_info->invalidate_regs[0] != LLDB_INVALID_REGNUM);
-
-    if (is_subreg) {
-      // Read the full aligned 64-bit register.
-      full_reg = reg_info->invalidate_regs[0];
     }
 
-    error = ReadRegisterRaw(full_reg, reg_value);
+    offset = reg_info->byte_offset;
+    assert(offset < GetGPRSize());
+    src = (uint8_t *)GetGPRBuffer() + offset;
 
-    if (error.Success()) {
-      // If our read was not aligned (for ah,bh,ch,dh), shift our returned
-      // value one byte to the right.
-      if (is_subreg && (reg_info->byte_offset & 0x1))
-        reg_value.SetUInt64(reg_value.GetAsUInt64() >> 8);
+  } else if (IsFPR(reg)) {
+    if (!m_fpu_is_valid) {
 
-      // If our return byte size was greater than the return value reg size,
-      // then use the type specified by reg_info rather than the uint64_t
-      // default
-      if (reg_value.GetByteSize() > reg_info->byte_size)
-        reg_value.SetType(reg_info);
-    }
+      error = ReadFPR();
+      if (error.Fail())
         return error;
     }
+    offset = CalculateFprOffset(reg_info);
+    assert(offset < GetFPRSize());
+    src = (uint8_t *)GetFPRBuffer() + offset;
+  } else
+    return Status("failed - register wasn't recognized to be a GPR or an FPR, "
+                  "write strategy unknown");
 
-  // Get pointer to m_fpr variable and set the data from it.
-  uint32_t fpr_offset = CalculateFprOffset(reg_info);
-  assert(fpr_offset < sizeof m_fpr);
-  uint8_t *src = (uint8_t *)&m_fpr + fpr_offset;
   reg_value.SetFromMemoryData(reg_info, src, reg_info->byte_size,
                               eByteOrderLittle, error);
 
   return error;
 }
 
 Status NativeRegisterContextLinux_arm64::WriteRegister(
     const RegisterInfo *reg_info, const RegisterValue &reg_value) {
+  Status error;
+
   if (!reg_info)
     return Status("reg_info NULL");
 
-  const uint32_t reg_index = reg_info->kinds[lldb::eRegisterKindLLDB];
-  if (reg_index == LLDB_INVALID_REGNUM)
+  const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
+
+  if (reg == LLDB_INVALID_REGNUM)
     return Status("no lldb regnum for %s", reg_info && reg_info->name
                                                ? reg_info->name
                                                : "<unknown register>");
 
-  if (IsGPR(reg_index))
-    return WriteRegisterRaw(reg_index, reg_value);
+  uint8_t *dst;
+  uint32_t offset;
 
-  if (IsFPR(reg_index)) {
-    // Get pointer to m_fpr variable and set the data to it.
-    uint32_t fpr_offset = CalculateFprOffset(reg_info);
-    assert(fpr_offset < sizeof m_fpr);
-    uint8_t *dst = (uint8_t *)&m_fpr + fpr_offset;
-    switch (reg_info->byte_size) {
-    case 2:
-      *(uint16_t *)dst = reg_value.GetAsUInt16();
-      break;
-    case 4:
-      *(uint32_t *)dst = reg_value.GetAsUInt32();
-      break;
-    case 8:
-      *(uint64_t *)dst = reg_value.GetAsUInt64();
-      break;
-    default:
-      assert(false && "Unhandled data size.");
-      return Status("unhandled register data size %" PRIu32,
-                    reg_info->byte_size);
+  if (IsGPR(reg)) {
+    if (!m_gpr_is_valid) {
+      error = ReadGPR();
+      if (error.Fail())
+        return error;
     }
 
-    Status error = WriteFPR();
+    offset = reg_info->byte_offset;
+    assert(offset < GetGPRSize());
+    dst = (uint8_t *)GetGPRBuffer() + offset;
+
+    ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
+
+    return WriteGPR();
+  } else if (IsFPR(reg)) {
+    if (!m_fpu_is_valid) {
+      error = ReadFPR();
       if (error.Fail())
         return error;
+    }
+    offset = CalculateFprOffset(reg_info);
+    assert(offset < GetFPRSize());
+    dst = (uint8_t *)GetFPRBuffer() + offset;
 
-    return Status();
+    ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
+
+    return WriteFPR();
   }
 
-  return Status("failed - register wasn't recognized to be a GPR or an FPR, "
-                "write strategy unknown");
+  return error;
 }
 
 Status NativeRegisterContextLinux_arm64::ReadAllRegisterValues(
     lldb::DataBufferSP &data_sp) {
   Status error;
 
   data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0));
+  if (!m_gpr_is_valid) {
     error = ReadGPR();
     if (error.Fail())
       return error;
+  }
 
+  if (!m_fpu_is_valid) {
     error = ReadFPR();
     if (error.Fail())
       return error;
-
+  }
   uint8_t *dst = data_sp->GetBytes();
-  ::memcpy(dst, &m_gpr_arm64, GetGPRSize());
+  ::memcpy(dst, GetGPRBuffer(), GetGPRSize());
   dst += GetGPRSize();
-  ::memcpy(dst, &m_fpr, sizeof(m_fpr));
+  ::memcpy(dst, GetFPRBuffer(), GetFPRSize());
 
   return error;
 }
 
 Status NativeRegisterContextLinux_arm64::WriteAllRegisterValues(
     const lldb::DataBufferSP &data_sp) {
   Status error;
 
   if (!data_sp) {
     error.SetErrorStringWithFormat(
         "NativeRegisterContextLinux_x86_64::%s invalid data_sp provided",
         __FUNCTION__);
     return error;
   }
 
   if (data_sp->GetByteSize() != REG_CONTEXT_SIZE) {
     error.SetErrorStringWithFormat(
         "NativeRegisterContextLinux_x86_64::%s data_sp contained mismatched "
         "data size, expected %" PRIu64 ", actual %" PRIu64,
         __FUNCTION__, REG_CONTEXT_SIZE, data_sp->GetByteSize());
     return error;
   }
 
   uint8_t *src = data_sp->GetBytes();
   if (src == nullptr) {
     error.SetErrorStringWithFormat("NativeRegisterContextLinux_x86_64::%s "
                                    "DataBuffer::GetBytes() returned a null "
                                    "pointer",
                                    __FUNCTION__);
     return error;
   }
-  ::memcpy(&m_gpr_arm64, src, GetRegisterInfoInterface().GetGPRSize());
+  ::memcpy(GetGPRBuffer(), src, GetRegisterInfoInterface().GetGPRSize());
 
   error = WriteGPR();
   if (error.Fail())
     return error;
 
   src += GetRegisterInfoInterface().GetGPRSize();
-  ::memcpy(&m_fpr, src, sizeof(m_fpr));
+  ::memcpy(GetFPRBuffer(), src, GetFPRSize());
 
   error = WriteFPR();
   if (error.Fail())
     return error;
 
   return error;
 }
 
for (uint32_t i = 0; i < m_max_hbp_supported; i++) {
       dreg_state.dbg_regs[i].ctrl = m_hbr_regs[i].control;
     }
   }
 
   return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(),
                                            &hwbType, &ioVec, ioVec.iov_len);
 }
 
-Status NativeRegisterContextLinux_arm64::DoReadRegisterValue(
-    uint32_t offset, const char *reg_name, uint32_t size,
-    RegisterValue &value) {
+Status NativeRegisterContextLinux_arm64::ReadGPR() {
   Status error;
-  if (offset > sizeof(struct user_pt_regs)) {
-    offset -= sizeof(struct user_pt_regs);
-    if (offset > sizeof(struct user_fpsimd_state)) {
-      error.SetErrorString("invalid offset value");
-      return error;
-    }
-    elf_fpregset_t regs;
-    int regset = NT_FPREGSET;
-    struct iovec ioVec;
 
-    ioVec.iov_base = &regs;
-    ioVec.iov_len = sizeof regs;
-    error = NativeProcessLinux::PtraceWrapper(
-        PTRACE_GETREGSET, m_thread.GetID(), &regset, &ioVec, sizeof regs);
-    if (error.Success()) {
-      value.SetBytes((void *)(((unsigned char *)(&regs)) + offset), 16,
-                     m_thread.GetProcess().GetByteOrder());
-    }
-  } else {
-    elf_gregset_t regs;
-    int regset = NT_PRSTATUS;
-    struct iovec ioVec;
 
-    ioVec.iov_base = &regs;
-    ioVec.iov_len = sizeof regs;
-    error = NativeProcessLinux::PtraceWrapper(
-        PTRACE_GETREGSET, m_thread.GetID(), &regset, &ioVec, sizeof regs);
-    if (error.Success()) {
-      value.SetBytes((void *)(((unsigned char *)(regs)) + offset), 8,
-                     m_thread.GetProcess().GetByteOrder());
-    }
-  }
-  return error;
-}
-
-Status NativeRegisterContextLinux_arm64::DoWriteRegisterValue(
-    uint32_t offset, const char *reg_name, const RegisterValue &value) {
-  Status error;
-  ::pid_t tid = m_thread.GetID();
-  if (offset > sizeof(struct user_pt_regs)) {
-    offset -= sizeof(struct user_pt_regs);
-    if (offset > sizeof(struct user_fpsimd_state)) {
-      error.SetErrorString("invalid offset value");
-      return error;
-    }
-    elf_fpregset_t regs;
-    int regset = NT_FPREGSET;
-    struct iovec ioVec;
+  ioVec.iov_base = GetGPRBuffer();
+  ioVec.iov_len = GetGPRSize();
 
-    ioVec.iov_base = &regs;
-    ioVec.iov_len = sizeof regs;
-    error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, &regset,
-                                              &ioVec, sizeof regs);
+  error = ReadRegisterSet(&ioVec, GetGPRSize(), NT_PRSTATUS);
 
-    if (error.Success()) {
-      ::memcpy((void *)(((unsigned char *)(&regs)) + offset), value.GetBytes(),
-               16);
-      error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, tid, &regset,
-                                                &ioVec, sizeof regs);
-    }
-  } else {
-    elf_gregset_t regs;
-    int regset = NT_PRSTATUS;
-    struct iovec ioVec;
+  if (error.Success())
+    m_gpr_is_valid = true;
 
-    ioVec.iov_base = &regs;
-    ioVec.iov_len = sizeof regs;
-    error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, &regset,
-                                              &ioVec, sizeof regs);
-    if (error.Success()) {
-      ::memcpy((void *)(((unsigned char *)(&regs)) + offset), value.GetBytes(),
-               8);
-      error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, tid, &regset,
-                                                &ioVec, sizeof regs);
-    }
-  }
   return error;
 }
 
-Status NativeRegisterContextLinux_arm64::ReadGPR() {
-  struct iovec ioVec;
-  ioVec.iov_base = GetGPRBuffer();
-  ioVec.iov_len = GetGPRSize();
-  return ReadRegisterSet(&ioVec, GetGPRSize(), NT_PRSTATUS);
-}
-
 Status NativeRegisterContextLinux_arm64::WriteGPR() {
   struct iovec ioVec;
+
+  m_gpr_is_valid = false;
+
   ioVec.iov_base = GetGPRBuffer();
   ioVec.iov_len = GetGPRSize();
+
   return WriteRegisterSet(&ioVec, GetGPRSize(), NT_PRSTATUS);
 }
 
 Status NativeRegisterContextLinux_arm64::ReadFPR() {
+  Status error;
+
   struct iovec ioVec;
+
   ioVec.iov_base = GetFPRBuffer();
   ioVec.iov_len = GetFPRSize();
-  return ReadRegisterSet(&ioVec, GetFPRSize(), NT_FPREGSET);
+
+  error = ReadRegisterSet(&ioVec, GetFPRSize(), NT_FPREGSET);
+
+  if (error.Success())
+    m_fpu_is_valid = true;
+
+  return error;
 }
 
 Status NativeRegisterContextLinux_arm64::WriteFPR() {
   struct iovec ioVec;
+
+  m_fpu_is_valid = false;
+
   ioVec.iov_base = GetFPRBuffer();
   ioVec.iov_len = GetFPRSize();
+
   return WriteRegisterSet(&ioVec, GetFPRSize(), NT_FPREGSET);
 }
 
+void NativeRegisterContextLinux_arm64::InvalidateAllRegisters() {
+  m_gpr_is_valid = false;
+  m_fpu_is_valid = false;
+}
+
 uint32_t NativeRegisterContextLinux_arm64::CalculateFprOffset(
     const RegisterInfo *reg_info) const {
   return reg_info->byte_offset -
          GetRegisterInfoAtIndex(m_reg_info.first_fpr)->byte_offset;
 }
 
 #endif // defined (__arm64__) || defined (__aarch64__)

lldb/source/Plugins/Process/Linux/NativeThreadLinux.cpp

if (m_hw_break_index_map.empty()) {
     }
   }
 
   intptr_t data = 0;
 
   if (signo != LLDB_INVALID_SIGNAL_NUMBER)
     data = signo;
 
+  // Before thread resumes, clear any cached register data structures
+  GetRegisterContext().InvalidateAllRegisters();
+
   return NativeProcessLinux::PtraceWrapper(PTRACE_CONT, GetID(), nullptr,
                                            reinterpret_cast<void *>(data));
 }
 
 Status NativeThreadLinux::SingleStep(uint32_t signo) {
   const StateType new_state = StateType::eStateStepping;
   MaybeLogStateChange(new_state);
   m_state = new_state;
   m_stop_info.reason = StopReason::eStopReasonNone;
 
   if(!m_step_workaround) {
     // If we already hava a workaround inplace, don't reset it. Otherwise, the
     // destructor of the existing instance will run after the new instance has
     // fetched the cpu mask, and the thread will end up with the wrong mask.
     m_step_workaround = SingleStepWorkaround::Get(m_tid);
   }
 
   intptr_t data = 0;
   if (signo != LLDB_INVALID_SIGNAL_NUMBER)
     data = signo;
 
+  // Before thread resumes, clear any cached register data structures
+  GetRegisterContext().InvalidateAllRegisters();
+
   // If hardware single-stepping is not supported, we just do a continue. The
   // breakpoint on the next instruction has been setup in
   // NativeProcessLinux::Resume.
   return NativeProcessLinux::PtraceWrapper(
       GetProcess().SupportHardwareSingleStepping() ? PTRACE_SINGLESTEP
                                                    : PTRACE_CONT,
       m_tid, nullptr, reinterpret_cast<void *>(data));
 }