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[SVE][AArch64] Adding pattern matching for some SVE instructions.
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Authored by mgudim on Oct 4 2019, 11:54 AM.

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Summary

This is a follow-up with https://reviews.llvm.org/D68098.

We added straight-forward patten matching for two SVE intrinsics: frecps and frsqrts. We also added patterns for fsub and fmul - these SDNodes directly correspond to machine instructions.

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Event Timeline

mgudim created this revision.Oct 4 2019, 11:54 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 4 2019, 11:54 AM
mgudim added inline comments.Oct 4 2019, 12:03 PM
llvm/include/llvm/IR/IntrinsicsAArch64.td
790–805

I will fix this before committing or in the next revision.

amehsan accepted this revision.Oct 9 2019, 8:26 AM

This looks straighforward. So LGTM. Since this is @mgudim's first patch, I will commit it for him. But I will wait a bit more (before committing) just in case @huntergr has any comments.

This revision is now accepted and ready to land.Oct 9 2019, 8:26 AM
huntergr accepted this revision.Oct 22 2019, 2:22 AM

Hi, thanks for waiting a bit. LGTM.

Hi, thanks for waiting a bit. LGTM.

Thanks @huntergr and Sorry for my delay. I will merge this very soon and get to the other patches. Thanks again.

huntergr added inline comments.Oct 29 2019, 3:32 AM
llvm/include/llvm/IR/IntrinsicsAArch64.td
856

One minor change I'd like to request is to do with the naming convention we have for these...

int_aarch64_sve_frecps_x and int_aarch64_sve_frsqrts_x would be the preferred names. Adding f to the start will match the instruction name, and the _x suffix is to indicate an unpredicated intrinsic.

mgudim updated this revision to Diff 226911.Oct 29 2019, 8:53 AM

Renamed the inrinsics according to the convention.

Renamed the inrinsics according to the convention.

Thanks :)