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Differential D68090

Fix doc for t inline asm constraints for ARM/Thumb
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Authored by pbarrio on Sep 26 2019, 9:20 AM.

Details

Reviewers
chill
Commits
rGffac4e860329: Fix doc for t inline asm constraints for ARM/Thumb
rL373228: Fix doc for t inline asm constraints for ARM/Thumb
Summary

The constraint goes up to regs d15 and q7, not d16 and q8.

Diff Detail

Event Timeline

pbarrio created this revision.Sep 26 2019, 9:20 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 26 2019, 9:20 AM
Herald added a subscriber: kristof.beyls. · View Herald Transcript
Harbormaster completed remote builds in B38610: Diff 221972.Sep 26 2019, 9:21 AM
pbarrio added a reviewer: chill.EditedSep 27 2019, 3:13 AM

Discussing with @chill on a chat, he was happier with the following wording:

A 32, 64, or 128-bit floating-point/SIMD register in the ranges s0-s31, d0-d31, or q0-q15, respectively.

And so forth. I will change these in all SIMD constraints (w, t, x) in both Thumb1 and ARM/Thumb2 modes.

pbarrio updated this revision to Diff 222203.Sep 27 2019, 10:46 AM

Reworded all the FP & SIMD constraints

Harbormaster completed remote builds in B38681: Diff 222203.Sep 27 2019, 10:47 AM
chill accepted this revision.Sep 30 2019, 1:55 AM
This revision is now accepted and ready to land.Sep 30 2019, 1:55 AM
Closed by commit rL373228: Fix doc for t inline asm constraints for ARM/Thumb (authored by pabbar01). · Explain WhySep 30 2019, 9:54 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

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docs/
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Diff 221972

llvm/docs/LangRef.rst

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- ``O``: Invalid immediate constraint. - ``O``: Invalid immediate constraint.
- ``r``: A general-purpose 32-bit integer register (``r0-r15``). - ``r``: A general-purpose 32-bit integer register (``r0-r15``).
- ``l``: In Thumb2 mode, low 32-bit GPR registers (``r0-r7``). In ARM mode, same - ``l``: In Thumb2 mode, low 32-bit GPR registers (``r0-r7``). In ARM mode, same
as ``r``. as ``r``.
- ``h``: In Thumb2 mode, a high 32-bit GPR register (``r8-r15``). In ARM mode, - ``h``: In Thumb2 mode, a high 32-bit GPR register (``r8-r15``). In ARM mode,
invalid. invalid.
- ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``, - ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``,
``d0-d31``, or ``q0-q15``. ``d0-d31``, or ``q0-q15``.
- ``t``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``,
``d0-d15``, or ``q0-q7``.
- ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``, - ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``,
``d0-d7``, or ``q0-q3``. ``d0-d7``, or ``q0-q3``.
- ``t``: A low floating-point/SIMD register: ``s0-s31``, ``d0-d16``, or
``q0-q8``.
ARM's Thumb1 mode: ARM's Thumb1 mode:
- ``I``: An immediate integer between 0 and 255. - ``I``: An immediate integer between 0 and 255.
- ``J``: An immediate integer between -255 and -1. - ``J``: An immediate integer between -255 and -1.
- ``K``: An immediate integer between 0 and 255, with optional left-shift by - ``K``: An immediate integer between 0 and 255, with optional left-shift by
some amount. some amount.
- ``L``: An immediate integer between -7 and 7. - ``L``: An immediate integer between -7 and 7.
- ``M``: An immediate integer which is a multiple of 4 between 0 and 1020. - ``M``: An immediate integer which is a multiple of 4 between 0 and 1020.
- ``N``: An immediate integer between 0 and 31. - ``N``: An immediate integer between 0 and 31.
- ``O``: An immediate integer which is a multiple of 4 between -508 and 508. - ``O``: An immediate integer which is a multiple of 4 between -508 and 508.
- ``r``: A low 32-bit GPR register (``r0-r7``). - ``r``: A low 32-bit GPR register (``r0-r7``).
- ``l``: A low 32-bit GPR register (``r0-r7``). - ``l``: A low 32-bit GPR register (``r0-r7``).
- ``h``: A high GPR register (``r0-r7``). - ``h``: A high GPR register (``r0-r7``).
- ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``, - ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``,
``d0-d31``, or ``q0-q15``. ``d0-d31``, or ``q0-q15``.
- ``t``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``,
``d0-d15``, or ``q0-q7``.
- ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``, - ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``,
``d0-d7``, or ``q0-q3``. ``d0-d7``, or ``q0-q3``.
- ``t``: A low floating-point/SIMD register: ``s0-s31``, ``d0-d16``, or
``q0-q8``.
Hexagon: Hexagon:
- ``o``, ``v``: A memory address operand, treated the same as constraint ``m``, - ``o``, ``v``: A memory address operand, treated the same as constraint ``m``,
at the moment. at the moment.
- ``r``: A 32 or 64-bit register. - ``r``: A 32 or 64-bit register.
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