[ARM][LowOverheadLoops] Use subs during revert.

[samparker]

Summary

Check whether there are any uses or defs between the LoopDec and LoopEnd. If there's not, then we can use a subs to set the cpsr and skip generating a cmp.

[dmgreen]

Is it possible for the CPSR to already be live? Live across the loop or something like it?

[samparker]

Not across the loop because LoopEnd implicitly defines it.

[dmgreen]

Nice. LGTM then.

llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

private:
     bool ProcessLoop(MachineLoop *ML);
 
     MachineInstr * IsSafeToDefineLR(MachineInstr *MI);
 
     bool RevertNonLoops();
 
     void RevertWhile(MachineInstr *MI) const;
 
-    void RevertLoopDec(MachineInstr *MI) const;
+    bool RevertLoopDec(MachineInstr *MI, bool AllowFlags = false) const;
 
-    void RevertLoopEnd(MachineInstr *MI) const;
+    void RevertLoopEnd(MachineInstr *MI, bool SkipCmp = false) const;
 
     void Expand(MachineLoop *ML, MachineInstr *Start,
                 MachineInstr *InsertPt, MachineInstr *Dec,
                 MachineInstr *End, bool Revert);
 
   };
 }
 
void ARMLowOverheadLoops::RevertWhile(MachineInstr *MI) const {
 
   MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
   MIB.add(MI->getOperand(1));   // branch target
   MIB.addImm(ARMCC::EQ);        // condition code
   MIB.addReg(ARM::CPSR);
   MI->eraseFromParent();
 }
 
-// TODO: Check flags so that we can possibly generate a tSubs or tSub.
-void ARMLowOverheadLoops::RevertLoopDec(MachineInstr *MI) const {
+bool ARMLowOverheadLoops::RevertLoopDec(MachineInstr *MI,
+                                        bool AllowFlags) const {
   LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to sub: " << *MI);
   MachineBasicBlock *MBB = MI->getParent();
+
+  // If nothing uses or defines CPSR between LoopDec and LoopEnd, use a t2SUBS.
+  bool SetFlags = false;
+  if (AllowFlags) {
+    if (auto *Def = SearchForDef(MI, MBB->end(), ARM::CPSR)) {
+      if (!SearchForUse(MI, MBB->end(), ARM::CPSR) &&
+          Def->getOpcode() == ARM::t2LoopEnd)
+        SetFlags = true;
+    }
+  }
+
   MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
                                     TII->get(ARM::t2SUBri));
   MIB.addDef(ARM::LR);
   MIB.add(MI->getOperand(1));
   MIB.add(MI->getOperand(2));
   MIB.addImm(ARMCC::AL);
   MIB.addReg(0);
+
+  if (SetFlags) {
+    MIB.addReg(ARM::CPSR);
+    MIB->getOperand(5).setIsDef(true);
+  } else
     MIB.addReg(0);
+
   MI->eraseFromParent();
+  return SetFlags;
 }
 
 // Generate a subs, or sub and cmp, and a branch instead of an LE.
-void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI) const {
+void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI, bool SkipCmp) const {
   LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp, br: " << *MI);
 
-  // Create cmp
   MachineBasicBlock *MBB = MI->getParent();
+  // Create cmp
+  if (!SkipCmp) {
     MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
                                       TII->get(ARM::t2CMPri));
     MIB.addReg(ARM::LR);
     MIB.addImm(0);
     MIB.addImm(ARMCC::AL);
     MIB.addReg(ARM::NoRegister);
+  }
 
   MachineBasicBlock *DestBB = MI->getOperand(1).getMBB();
   unsigned BrOpc = BBUtils->isBBInRange(MI, DestBB, 254) ?
     ARM::tBcc : ARM::t2Bcc;
 
   // Create bne
-  MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
+  MachineInstrBuilder MIB =
+    BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
   MIB.add(MI->getOperand(1));   // branch target
   MIB.addImm(ARMCC::NE);        // condition code
   MIB.addReg(ARM::CPSR);
   MI->eraseFromParent();
 }
 
 void ARMLowOverheadLoops::Expand(MachineLoop *ML, MachineInstr *Start,
                                  MachineInstr *InsertPt,
auto RemoveDeadBranch = [](MachineInstr *I) {
     }
   };
 
   if (Revert) {
     if (Start->getOpcode() == ARM::t2WhileLoopStart)
       RevertWhile(Start);
     else
       Start->eraseFromParent();
-    RevertLoopDec(Dec);
-    RevertLoopEnd(End);
+    bool FlagsAlreadySet = RevertLoopDec(Dec, true);
+    RevertLoopEnd(End, FlagsAlreadySet);
   } else {
     Start = ExpandLoopStart(ML, Start, InsertPt);
     RemoveDeadBranch(Start);
     End = ExpandLoopEnd(ML, Dec, End);
     RemoveDeadBranch(End);
   }
 }
 

llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll

 ; RUN: llc -mtriple=thumbv8.1m.main -O0 -mattr=+lob -disable-arm-loloops=false -stop-before=arm-low-overhead-loops %s -o - | FileCheck %s --check-prefix=CHECK-MID
 ; RUN: llc -mtriple=thumbv8.1m.main -O0 -mattr=+lob -disable-arm-loloops=false -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-END
 
 ; Test that the branch targets are correct after isel, even though the loop
 ; will sometimes be reverted anyway.
 
 ; CHECK-MID: name: check_loop_dec_brcond_combine
 ; CHECK-MID: bb.2.for.body:
 ; CHECK-MID:   renamable $lr = t2LoopDec killed renamable $lr, 1
 ; CHECK-MID:   t2LoopEnd killed renamable $lr, %bb.3
 ; CHECK-MID: bb.3.for.header:
 ; CHECK-MID:   tB %bb.2
 
 ; CHECK-END: .LBB0_1:
 ; CHECK-END:   b .LBB0_3
 ; CHECK-END: .LBB0_2:
-; CHECK-END:   sub.w lr, lr, #1
-; CHECK-END:   cmp.w lr, #0
+; CHECK-END:   subs.w lr, lr, #1
 ; CHECK-END:   bne .LBB0_3
 ; CHECK-END:   b .LBB0_4
 ; CHECK-END: .LBB0_3:
 ; CHECK-END:   b .LBB0_2
 define void @check_loop_dec_brcond_combine(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) {
 entry:
   call void @llvm.set.loop.iterations.i32(i32 %N)
   br label %for.body.preheader

llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir

 # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
 
 # CHECK-NOT: DoLoopStart
 # CHECK-NOT: DLS
 # CHECK: bb.1.for.body:
-# CHECK:   t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
-# CHECK:   tBcc %bb.3, 1, $cpsr
-# CHECK:   tB %bb.2, 14, $noreg
+# CHECK:      $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr
+# CHECK-NOT:  t2CMPri $lr
+# CHECK:      tBcc %bb.3, 1, $cpsr
+# CHECK:      tB %bb.2, 14, $noreg
 # CHECK: bb.2.for.cond.cleanup:
 # CHECK: bb.3.for.header:
 
 --- |
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
   
   define void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) {

llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir

 # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
 # CHECK-NOT: t2DLS
 # CHECK: bb.5.for.inc16:
-# CHECK:   $lr = t2SUBri killed renamable $lr, 1, 14
-# CHECK:   t2CMPri $lr, 0, 14
-# CHECK:   tBcc %bb.6, 1
-# CHECK:   tB %bb.2
+# CHECK:      $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr
+# CHECK-NOT:  t2CMPri $lr
+# CHECK:      tBcc %bb.6, 1
+# CHECK:      tB %bb.2
 # CHECK: bb.6.for.cond4.preheader:
 
 --- |
   ; ModuleID = 'revert-non-header.ll'
   source_filename = "revert-non-header.ll"
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
   

llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir

 # RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
 # CHECK:      body:
 # CHECK:      bb.0.entry:
 # CHECK:        t2CMPri $r3, 0, 14
 # CHECK-NEXT:   t2Bcc %bb.3, 0, $cpsr
 # CHECK-NEXT:   tB %bb.1
 # CHECK:      bb.1.do.body.preheader:
 # CHECK:        $lr = tMOVr killed $r3
 # CHECK:      bb.2.do.body:
-# CHECK:        $lr = t2SUBri killed renamable $lr, 1, 14
-# CHECK-NEXT:   t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
+# CHECK:        $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr
 # CHECK-NEXT:   t2Bcc %bb.2, 1, $cpsr
 # CHECK-NEXT:   tB %bb.3, 14
 
 --- |
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
   
   define void @ne_trip_count(i1 zeroext %t1, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) #0 {