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[X86][SSE] Add support for <64 x i1> bool reduction
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Authored by RKSimon on Mon, Sep 2, 4:36 AM.

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Summary

This generalizes the existing <32 x i1> pre-AVX2 split code to support reductions from <64 x i1> as well, we can probably generalize to any larger pow2 case in the future if the (unlikely) need ever arises.

We still need to tweak combineBitcastvxi1 to improve AVX512F codegen as its assumes vXi1 types should be handled on the mask registers even when they aren't legal.

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rL LLVM

Event Timeline

RKSimon created this revision.Mon, Sep 2, 4:36 AM
Herald added a project: Restricted Project. · View Herald TranscriptMon, Sep 2, 4:36 AM
craig.topper added inline comments.Thu, Sep 5, 2:54 PM
test/CodeGen/X86/vector-reduce-and-bool.ll
842 ↗(On Diff #218329)

Can we do something to fix this case?

RKSimon added inline comments.Fri, Sep 6, 1:48 AM
test/CodeGen/X86/vector-reduce-and-bool.ll
842 ↗(On Diff #218329)

Yup, combineBitcastvxi1 needs some tweaking to better handle this. I'm happy to do this before or after this patch but they are separate improvements.

This revision is now accepted and ready to land.Sat, Sep 7, 6:30 PM
This revision was automatically updated to reflect the committed changes.