[TableGen] Emit OperandType enums for RegisterOperands/RegisterClasses

[nlguillemot]

Summary

The OpTypes::OperandType was creating an enum for all records that inherit from
Operand, but in reality there are operands for instructions that inherit from
other types too. In particular, RegisterOperand and RegisterClass. This
commit adds those types to the list of operand types that are tracked by
the OperandType enum.

[dsanders]

utils/TableGen/InstrInfoEmitter.cpp

347–355

Wouldn't it be simpler to have:

for (const std::vector<Record *> &CurrentVec
        : { &Operands, &RegisterOperands, &RegisterClasses }) {
  for (const Record *Op : CurrentVec) {

[nlguillemot]

utils/TableGen/InstrInfoEmitter.cpp

347–355

I think my thought process at the time was that I didn't want to "hard code" the fact that the data comes from a vector... but yeah it's complex and I think I like your suggestion better.

[dsanders]

LGTM with that change

[nlguillemot]

Refactored loop over the list of vectors to avoid the tricky array/pointer loops.

[aditya_nandakumar]

Committed revision 372641

test/TableGen/get-operand-type.td

 }
 
 def Reg : Register<"reg">;
 def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
 
 def OpA : Operand<i32>;
 def OpB : Operand<i32>;
 
+def RegOp : RegisterOperand<RegClass>;
+
 def InstA : Instruction {
   let Size = 1;
   let OutOperandList = (outs OpA:$a);
   let InOperandList = (ins OpB:$b, i32imm:$c);
   field bits<8> Inst;
   field bits<8> SoftFail = 0;
   let Namespace = "MyNamespace";
 }
 
 def InstB : Instruction {
   let Size = 1;
   let OutOperandList = (outs i32imm:$d);
   let InOperandList = (ins unknown:$x);
   field bits<8> Inst;
   field bits<8> SoftFail = 0;
   let Namespace = "MyNamespace";
 }
 
+def InstC : Instruction {
+  let Size = 1;
+  let OutOperandList = (outs RegClass:$d);
+  let InOperandList = (ins RegOp:$x);
+  field bits<8> Inst;
+  field bits<8> SoftFail = 0;
+  let Namespace = "MyNamespace";
+}
+
 // CHECK: #ifdef GET_INSTRINFO_OPERAND_TYPE
 // CHECK:        OpTypes::OpA, OpTypes::OpB, OpTypes::i32imm,
 // CHECK-NEXT:   OpTypes::i32imm, -1,
-// CHECK: #endif //GET_INSTRINFO_OPERAND_TYPE
+// CHECK-NEXT:   OpTypes::RegClass, OpTypes::RegOp,
+// CHECK: #endif // GET_INSTRINFO_OPERAND_TYPE

utils/TableGen/InstrInfoEmitter.cpp

 /// llvm::TargetNamespace::OpTypes namespace.
 /// Operand types are all definitions derived of the Operand Target.td class.
 void InstrInfoEmitter::emitOperandTypeMappings(
     raw_ostream &OS, const CodeGenTarget &Target,
     ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
 
   StringRef Namespace = Target.getInstNamespace();
   std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
+  std::vector<Record *> RegisterOperands =
+      Records.getAllDerivedDefinitions("RegisterOperand");
+  std::vector<Record *> RegisterClasses =
+      Records.getAllDerivedDefinitions("RegisterClass");
 
   OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
   OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
   OS << "namespace llvm {\n";
   OS << "namespace " << Namespace << " {\n";
   OS << "namespace OpTypes {\n";
   OS << "enum OperandType {\n";
 
   unsigned EnumVal = 0;
-  for (const Record *Op : Operands) {
+  for (const std::vector<Record *> *RecordsToAdd :
+       {&Operands, &RegisterOperands, &RegisterClasses}) {
+    for (const Record *Op : *RecordsToAdd) {
       if (!Op->isAnonymous())
         OS << "  " << Op->getName() << " = " << EnumVal << ",\n";
       ++EnumVal;
     }
+  }
 
   OS << "  OPERAND_TYPE_LIST_END" << "\n};\n";
   OS << "} // end namespace OpTypes\n";
   OS << "} // end namespace " << Namespace << "\n";
   OS << "} // end namespace llvm\n";
   OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n";
 
   OS << "#ifdef GET_INSTRINFO_OPERAND_TYPE\n";
   OS << "#undef GET_INSTRINFO_OPERAND_TYPE\n";
   OS << "namespace llvm {\n";
   OS << "namespace " << Namespace << " {\n";
   OS << "LLVM_READONLY\n";
-  OS << "int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
+  OS << "static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
+  // TODO: Factor out instructions with same operands to compress the tables.
   if (!NumberedInstructions.empty()) {
     std::vector<int> OperandOffsets;
     std::vector<Record *> OperandRecords;
     int CurrentOffset = 0;
     for (const CodeGenInstruction *Inst : NumberedInstructions) {
       OperandOffsets.push_back(CurrentOffset);
       for (const auto &Op : Inst->Operands) {
         const DagInit *MIOI = Op.MIOperandInfo;
for (int I = 0, E = OperandRecords.size(), CurOffset = 1; I != E; ++I) {
       // We print each Opcode's operands in its own row.
       if (I == OperandOffsets[CurOffset]) {
         OS << "\n    ";
         // If there are empty rows, mark them with an empty comment.
         while (OperandOffsets[++CurOffset] == I)
           OS << "/**/\n    ";
       }
       Record *OpR = OperandRecords[I];
-      if (OpR->isSubClassOf("Operand") && !OpR->isAnonymous())
+      if ((OpR->isSubClassOf("Operand") ||
+           OpR->isSubClassOf("RegisterOperand") ||
+           OpR->isSubClassOf("RegisterClass")) &&
+          !OpR->isAnonymous())
         OS << "OpTypes::" << OpR->getName();
       else
         OS << -1;
       OS << ", ";
     }
     OS << "\n  };\n";
 
     OS << "  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];\n";
   } else {
     OS << "  llvm_unreachable(\"No instructions defined\");\n";
   }
   OS << "}\n";
   OS << "} // end namespace " << Namespace << "\n";
   OS << "} // end namespace llvm\n";
-  OS << "#endif //GET_INSTRINFO_OPERAND_TYPE\n\n";
+  OS << "#endif // GET_INSTRINFO_OPERAND_TYPE\n\n";
 }
 
 void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,
                                              StringRef TargetName) {
   RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
   if (TIIPredicates.empty())
     return;