[PeepholeOptimizer] Don't assume bitcast def always has input

[jsji]

Summary

If we have a MI marked with bitcast bits, but without input operands,
PeepholeOptimizer might crash with assert.

eg:
If we apply the changes in PPCInstrVSX.td as in this patch:

[(set v4i32:$XT, (bitconvert (v16i8 immAllOnesV)))]>;

We will get assert in PeepholeOptimizer.

llvm-lit llvm-project/llvm/test/CodeGen/PowerPC/bitcast-peelhole.ll -v

llvm-project/llvm/include/llvm/CodeGen/MachineInstr.h:417: const
llvm::MachineOperand &llvm::MachineInstr::getOperand(unsigned int)
const: Assertion `i < getNumOperands() && "getOperand() out of range!"'
failed.

The fix is to abort if we found out of bound access.

[jsji]

arc command mistake.

llvm/lib/CodeGen/PeepholeOptimizer.cpp

if (MO.isImplicit() && MO.isDead())
       continue;
     assert(!MO.isDef() && "We should have skipped all the definitions by now");
     if (SrcIdx != EndOpIdx)
       // Multiple sources?
       return ValueTrackerResult();
     SrcIdx = OpIdx;
   }
 
+  // In some rare case, Def has no input, SrcIdx is out of bound,
+  // getOperand(SrcIdx) will fail below.
+  if (SrcIdx >= Def->getNumOperands())
+    return ValueTrackerResult();
+
   // Stop when any user of the bitcast is a SUBREG_TO_REG, replacing with a COPY
   // will break the assumed guarantees for the upper bits.
   for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg())) {
     if (UseMI.isSubregToReg())
       return ValueTrackerResult();
   }
 
   const MachineOperand &Src = Def->getOperand(SrcIdx);

llvm/lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
 
   def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B),
             (XXLEQV $A, $B)>;
 
   let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
       isReMaterializable = 1 in {
     def XXLEQVOnes : XX3Form_SameOp<60, 186, (outs vsrc:$XT), (ins),
                          "xxleqv $XT, $XT, $XT", IIC_VecGeneral,
-                         [(set v4i32:$XT, (v4i32 immAllOnesV))]>;
+                         [(set v4i32:$XT, (bitconvert (v16i8 immAllOnesV)))]>;
   }
 
   def XXLORC : XX3Form<60, 170,
                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
                        "xxlorc $XT, $XA, $XB", IIC_VecGeneral,
                        [(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>;
 
   // VSX scalar loads introduced in ISA 2.07
def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
                   (MTVSRD (RLDIMI AnyExts.C, AnyExts.D, 32, 0)), VSRC),
                 (COPY_TO_REGCLASS
                   (MTVSRD (RLDIMI AnyExts.A, AnyExts.B, 32, 0)), VSRC), 0)>;
     def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
               (XXSPLTW (COPY_TO_REGCLASS (MTVSRWZ $A), VSRC), 1)>;
   }
 
   let Predicates = [HasP8Vector] in {
-    def : Pat<(v4i32 (bitconvert (v16i8 immAllOnesV))),
-              (XXLEQVOnes)>;
     def : Pat<(v1i128 (bitconvert (v16i8 immAllOnesV))),
               (v1i128 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
     def : Pat<(v2i64 (bitconvert (v16i8 immAllOnesV))),
               (v2i64 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
     def : Pat<(v8i16 (bitconvert (v16i8 immAllOnesV))),
               (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
     def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
               (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;

llvm/test/CodeGen/PowerPC/bitcast-peelhole.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; REQUIRES: asserts
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+
+define < 4 x i32> @bitCast() {
+; CHECK-LABEL: bitCast:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxleqv v2, v2, v2
+; CHECK-NEXT:    blr
+entry:
+  ret < 4 x i32> <i32 -1, i32 -1,i32 -1,i32 -1 >
+}