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[AArch64][GlobalISel] Select patterns which use shifted register operands

Authored by paquette on Aug 13 2019, 1:50 PM.



This adds GlobalISel equivalents for the following from AArch64InstrFormats:

  • arith_shifted_reg32
  • arith_shifted_reg64

And partial support for

  • logical_shifted_reg32
  • logical_shifted_reg32

The only thing missing for the logical cases is support for rotates. Other than the missing support, the transformation is identical for the arithmetic shifted register and the logical shifted register.

Lots of tests here:

  • Add select-arith-shifted-reg.mir to show that we correctly select add and

sub instructions which use this pattern.

  • Add select-logical-shifted-reg.mir to cover patterns which are not shared

between the arithmetic and logical cases.

  • Update addsub-shifted.ll to show that we correctly fold shifts into


  • Update eon.ll to show that we can select the eon instruction by folding xors.

Diff Detail


Event Timeline

paquette created this revision.Aug 13 2019, 1:50 PM
aemerson added inline comments.Aug 13 2019, 2:23 PM
4553 ↗(On Diff #214910)

Can simplify this a bit to MRI.getType(ShiftReg).getSizeInBits();

37 ↗(On Diff #214910)

The checks here are identical to the rhs case. Should we be trying to test a less degenerate case? Like:

%0:gpr(s64) = COPY $x0
%param2:gpr(s64) = COPY $x1
%1:gpr(s64) = G_CONSTANT i64 8
%2:gpr(s64) = G_SHL %0, %1:gpr(s64)
%3:gpr(s64) = G_ADD %2, %param2:gpr(s64)
paquette updated this revision to Diff 214932.Aug 13 2019, 2:54 PM
paquette marked 2 inline comments as done.

Improve LHS test cases and simplify NumBits calculation

aemerson accepted this revision.Aug 13 2019, 3:03 PM


This revision is now accepted and ready to land.Aug 13 2019, 3:03 PM
This revision was automatically updated to reflect the committed changes.