AMDGPU: Don't assert on v4f16 arguments to shader calling conventions

[nhaehnle]

LGTM

[arsenm]

r367018

lib/Target/AMDGPU/SIISelLowering.cpp

if (CallConv == CallingConv::AMDGPU_PS &&
         !Arg->Flags.isInReg() && PSInputNum <= 15) {
       bool SkipArg = !Arg->Used && !Info->isPSInputAllocated(PSInputNum);
 
       // Inconveniently only the first part of the split is marked as isSplit,
       // so skip to the end. We only want to increment PSInputNum once for the
       // entire split argument.
       if (Arg->Flags.isSplit()) {
         while (!Arg->Flags.isSplitEnd()) {
-          assert(!Arg->VT.isVector() &&
+          assert((!Arg->VT.isVector() ||
+                  Arg->VT.getScalarSizeInBits() == 16) &&
                  "unexpected vector split in ps argument type");
           if (!SkipArg)
             Splits.push_back(*Arg);
           Arg = &Ins[++I];
         }
       }
 
       if (SkipArg) {

test/CodeGen/AMDGPU/calling-conventions.ll

 ; SI: s_or_b32 s0, s1, s0
 ; SI: s_add_i32 s0, s0, 0x10000
 define amdgpu_ps void @ps_mesa_inreg_v2i16(<2 x i16> inreg %arg0) {
   %add = add <2 x i16> %arg0, <i16 1, i16 1>
   store <2 x i16> %add, <2 x i16> addrspace(1)* undef
   ret void
 }
 
+; FIXME: Differenet ABI for VI+
+; GCN-LABEL: {{^}}ps_mesa_v4f16:
+; SI: v_cvt_f16_f32_e32 v3, v3
+; SI: v_cvt_f16_f32_e32 v2, v2
+; SI: v_cvt_f16_f32_e32 v1, v1
+; SI: v_cvt_f16_f32_e32 v0, v0
+
+; VI: v_add_f16_e32 v2, 1.0, v1
+; VI: v_add_f16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI: v_add_f16_e32 v4, 1.0, v0
+; VI: v_add_f16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+define amdgpu_ps <4 x half> @ps_mesa_v4f16(<4 x half> %arg0) {
+  %add = fadd <4 x half> %arg0, <half 1.0, half 1.0, half 1.0, half 1.0>
+  ret <4 x half> %add
+}
+
+; GCN-LABEL: {{^}}ps_mesa_inreg_v4f16:
+; SI: v_cvt_f16_f32_e32 v{{[0-9]+}}, s3
+; SI: v_cvt_f16_f32_e32 v{{[0-9]+}}, s2
+; SI: v_cvt_f16_f32_e32 v{{[0-9]+}}, s1
+; SI: v_cvt_f16_f32_e32 v{{[0-9]+}}, s0
+
+; VI: v_add_f16_e64
+; VI: v_add_f16_sdwa
+; VI: v_add_f16_e64
+; VI: v_add_f16_sdwa
+define amdgpu_ps <4 x half> @ps_mesa_inreg_v4f16(<4 x half> inreg %arg0) {
+  %add = fadd <4 x half> %arg0, <half 1.0, half 1.0, half 1.0, half 1.0>
+  ret <4 x half> %add
+}
+
 ; GCN-LABEL: {{^}}ps_mesa_inreg_v3i32:
 ; GCN-DAG: s_add_i32 s0, s0, 1
 ; GCN-DAG: s_add_i32 s{{[0-9]*}}, s1, 2
 ; GCN-DAG: s_add_i32 s{{[0-9]*}}, s2, 3
 define amdgpu_ps void @ps_mesa_inreg_v3i32(<3 x i32> inreg %arg0) {
   %add = add <3 x i32> %arg0, <i32 1, i32 2, i32 3>
   store <3 x i32> %add, <3 x i32> addrspace(1)* undef
   ret void