[AMDGPU] Drop Reg32 and use regular AsmName

[rampitec]

Summary

This allows to reduce generated AMDGPUGenAsmWriter.inc by ~100Kb.

[arsenm]

LGTM

lib/Target/AMDGPU/SIRegisterInfo.td

58 ↗

(On Diff #210685)

I noticed this is giving extra names to m0

[rampitec]

lib/Target/AMDGPU/SIRegisterInfo.td

58 ↗

(On Diff #210685)

Right, all registers in a class must support all altNameIndexes supported by that class. Thus special registers need to have names at every slot.

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

case AMDGPU::PRIVATE_RSRC_REG:
     llvm_unreachable("pseudo-register should not ever be emitted");
   case AMDGPU::SCC:
     llvm_unreachable("pseudo scc should not ever be emitted");
   default:
     break;
   }
 #endif
 
-  unsigned AltName = AMDGPU::Reg32;
+  unsigned AltName = AMDGPU::NoRegAltName;
 
   if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(RegNo) ||
       MRI.getRegClass(AMDGPU::SGPR_64RegClassID).contains(RegNo) ||
       MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(RegNo))
     AltName = AMDGPU::Reg64;
   else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(RegNo) ||
            MRI.getRegClass(AMDGPU::SGPR_128RegClassID).contains(RegNo) ||
            MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(RegNo))

llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp

 }
 
 StringRef SIRegisterInfo::getRegAsmName(unsigned Reg) const {
   const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
   unsigned Size = getRegSizeInBits(*RC);
   unsigned AltName = AMDGPU::NoRegAltName;
 
   switch (Size) {
-  case 32:   AltName = AMDGPU::Reg32; break;
   case 64:   AltName = AMDGPU::Reg64; break;
   case 96:   AltName = AMDGPU::Reg96; break;
   case 128:  AltName = AMDGPU::Reg128; break;
   case 160:  AltName = AMDGPU::Reg160; break;
   case 256:  AltName = AMDGPU::Reg256; break;
   case 512:  AltName = AMDGPU::Reg512; break;
   case 1024: AltName = AMDGPU::Reg1024; break;
   }

llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td

list<SubRegIndex> ret = !if(!eq(size, 2), ret2,
                                   !if(!eq(size, 4), ret4,
                                       !if(!eq(size, 5), ret5,
                                           !if(!eq(size, 8), ret8,
                                               !if(!eq(size, 16), ret16, ret32))))));
 }
 
 let Namespace = "AMDGPU" in {
 defset list<RegAltNameIndex> AllRegAltNameIndices = {
-  def Reg32   : RegAltNameIndex;
   def Reg64   : RegAltNameIndex;
   def Reg96   : RegAltNameIndex;
   def Reg128  : RegAltNameIndex;
   def Reg160  : RegAltNameIndex;
   def Reg256  : RegAltNameIndex;
   def Reg512  : RegAltNameIndex;
   def Reg1024 : RegAltNameIndex;
 }
 }
 
 //===----------------------------------------------------------------------===//
 //  Declarations that describe the SI registers
 //===----------------------------------------------------------------------===//
 class SIReg <string n, bits<16> regIdx = 0, string prefix = "",
              int regNo = !cast<int>(regIdx)> :
   Register<n, !if(!eq(prefix, ""),
-                [ n, n, n, n, n, n, n, n ],
-                [ prefix # regNo,
-                  prefix # "[" # regNo # ":" # !and(!add(regNo, 1), 255) # "]",
+                [ n, n, n, n, n, n, n ],
+                [ prefix # "[" # regNo # ":" # !and(!add(regNo, 1), 255) # "]",
                   prefix # "[" # regNo # ":" # !and(!add(regNo, 2), 255) # "]",
                   prefix # "[" # regNo # ":" # !and(!add(regNo, 3), 255) # "]",
                   prefix # "[" # regNo # ":" # !and(!add(regNo, 4), 255) # "]",
                   prefix # "[" # regNo # ":" # !and(!add(regNo, 7), 255) # "]",
                   prefix # "[" # regNo # ":" # !and(!add(regNo, 15), 255) # "]",
                   prefix # "[" # regNo # ":" # !and(!add(regNo, 31), 255) # "]",
                 ])>,
   DwarfRegNum<[!cast<int>(HWEncoding)]> {
   let Namespace = "AMDGPU";
   let RegAltNameIndices = AllRegAltNameIndices;
 
   // This is the not yet the complete register encoding. An additional
   // bit is set for VGPRs.
   let HWEncoding = regIdx;
 }
 
 class SIRegisterWithSubRegs<string n, list<Register> subregs> :
   RegisterWithSubRegs<n, subregs> {
   let RegAltNameIndices = AllRegAltNameIndices;
-  let AltNames = [ n, n, n, n, n, n, n, n ];
+  let AltNames = [ n, n, n, n, n, n, n ];
 }
 
 // Special Registers
 def VCC_LO : SIReg<"vcc_lo", 106>;
 def VCC_HI : SIReg<"vcc_hi", 107>;
 
 // Pseudo-registers: Used as placeholders during isel and immediately
 // replaced, never seeing the verifier.

 defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes.
 
 def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>;
 def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>;
 def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;
 
 // SGPR registers
 foreach Index = 0-105 in {
-  def SGPR#Index : SIReg <"SGPR"#Index, Index, "s">;
+  def SGPR#Index : SIReg <"s"#Index, Index, "s">;
 }
 
 // VGPR registers
 foreach Index = 0-255 in {
-  def VGPR#Index : SIReg <"VGPR"#Index, Index, "v"> {
+  def VGPR#Index : SIReg <"v"#Index, Index, "v"> {
     let HWEncoding{8} = 1;
   }
 }
 
 // AccVGPR registers
 foreach Index = 0-255 in {
-  def AGPR#Index : SIReg <"AGPR"#Index, Index, "a"> {
+  def AGPR#Index : SIReg <"a"#Index, Index, "a"> {
     let HWEncoding{8} = 1;
   }
 }
 
 //===----------------------------------------------------------------------===//
 //  Groupings using register classes and tuples
 //===----------------------------------------------------------------------===//
 
 def SCC_CLASS : RegisterClass<"AMDGPU", [i1], 1, (add SCC)> {
   let CopyCost = -1;
   let isAllocatable = 0;
 }
 
 def M0_CLASS : RegisterClass<"AMDGPU", [i32], 32, (add M0)> {
   let CopyCost = 1;
   let isAllocatable = 0;
 }
 
 // TODO: Do we need to set DwarfRegAlias on register tuples?
 
 // SGPR 32-bit registers
 def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
-                            (add (sequence "SGPR%u", 0, 105)), Reg32> {
+                            (add (sequence "SGPR%u", 0, 105))> {
   // Give all SGPR classes higher priority than VGPR classes, because
   // we want to spill SGPRs to VGPRs.
   let AllocationPriority = 9;
 }
 
 // SGPR 64-bit registers
 def SGPR_64Regs : RegisterTuples<getSubRegs<2>.ret,
                              [(add (decimate SGPR_32, 2)),
TmpRegTuplesBase<0, 16,
                    [TTMP0_gfx9_gfx10, TTMP1_gfx9_gfx10, TTMP2_gfx9_gfx10, TTMP3_gfx9_gfx10,
                     TTMP4_gfx9_gfx10, TTMP5_gfx9_gfx10, TTMP6_gfx9_gfx10, TTMP7_gfx9_gfx10,
                     TTMP8_gfx9_gfx10, TTMP9_gfx9_gfx10, TTMP10_gfx9_gfx10, TTMP11_gfx9_gfx10,
                     TTMP12_gfx9_gfx10, TTMP13_gfx9_gfx10, TTMP14_gfx9_gfx10, TTMP15_gfx9_gfx10]>;
 
 // VGPR 32-bit registers
 // i16/f16 only on VI+
 def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
-                            (add (sequence "VGPR%u", 0, 255)), Reg32> {
+                            (add (sequence "VGPR%u", 0, 255))> {
   let AllocationPriority = 1;
   let Size = 32;
 }
 
 // VGPR 64-bit registers
 def VGPR_64 : RegisterTuples<getSubRegs<2>.ret,
                              [(add (trunc VGPR_32, 255)),
                               (add (shl VGPR_32, 1))]>;
def VGPR_1024 : RegisterTuples<getSubRegs<32>.ret,
                                (add (shl VGPR_32, 27)),
                                (add (shl VGPR_32, 28)),
                                (add (shl VGPR_32, 29)),
                                (add (shl VGPR_32, 30)),
                                (add (shl VGPR_32, 31))]>;
 
 // AccVGPR 32-bit registers
 def AGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
-                            (add (sequence "AGPR%u", 0, 255)), Reg32> {
+                            (add (sequence "AGPR%u", 0, 255))> {
   let AllocationPriority = 1;
   let Size = 32;
 }
 
 // AGPR 64-bit registers
 def AGPR_64 : RegisterTuples<getSubRegs<2>.ret,
                              [(add (trunc AGPR_32, 255)),
                               (add (shl AGPR_32, 1))]>;
def AGPR_1024 : RegisterTuples<getSubRegs<32>.ret,
                                (add (shl AGPR_32, 30)),
                                (add (shl AGPR_32, 31))]>;
 
 //===----------------------------------------------------------------------===//
 //  Register classes used as source and destination
 //===----------------------------------------------------------------------===//
 
 def Pseudo_SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
-  (add FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG), Reg32> {
+  (add FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG)> {
   let isAllocatable = 0;
   let CopyCost = -1;
 }
 
 def Pseudo_SReg_128 : RegisterClass<"AMDGPU", [v4i32, v2i64, v2f64], 32,
   (add PRIVATE_RSRC_REG), Reg128> {
   let isAllocatable = 0;
   let CopyCost = -1;
 }
 
 def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
-  (add LDS_DIRECT), Reg32> {
+  (add LDS_DIRECT)> {
   let isAllocatable = 0;
   let CopyCost = -1;
 }
 
 // Subset of SReg_32 without M0 for SMRD instructions and alike.
 // See comments in SIInstructions.td for more info.
 def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
   (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI,
    SGPR_NULL, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT,
    SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, SRC_POPS_EXITING_WAVE_ID,
-   SRC_VCCZ, SRC_EXECZ, SRC_SCC), Reg32> {
+   SRC_VCCZ, SRC_EXECZ, SRC_SCC)> {
   let AllocationPriority = 10;
 }
 
 def SReg_32_XEXEC_HI : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
-  (add SReg_32_XM0_XEXEC, EXEC_LO, M0_CLASS), Reg32> {
+  (add SReg_32_XM0_XEXEC, EXEC_LO, M0_CLASS)> {
   let AllocationPriority = 10;
 }
 
 def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
-  (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI), Reg32> {
+  (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> {
   let AllocationPriority = 10;
 }
 
 // Register class for all scalar registers (SGPRs + Special Registers)
 def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
-  (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI), Reg32> {
+  (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI)> {
   let AllocationPriority = 10;
 }
 
 def SRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
-  (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI, LDS_DIRECT_CLASS),
-  Reg32> {
+  (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI, LDS_DIRECT_CLASS)> {
   let isAllocatable = 0;
 }
 
 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32,
                             (add SGPR_64Regs), Reg64> {
   let CopyCost = 1;
   let AllocationPriority = 11;
 }

 def SReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
                              (add SGPR_512, TTMP_512), Reg512> {
   // Requires 8 s_mov_b64 to copy
   let CopyCost = 8;
   let AllocationPriority = 18;
 }
 
 def VRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
-                                 (add VGPR_32, LDS_DIRECT_CLASS), Reg32> {
+                                 (add VGPR_32, LDS_DIRECT_CLASS)> {
   let isAllocatable = 0;
 }
 
 def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
                               (add SGPR_1024Regs), Reg1024> {
   let AllocationPriority = 19;
 }
 

 
 def AReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
                               (add AGPR_1024), Reg1024> {
   let Size = 1024;
   let CopyCost = 65;
   let AllocationPriority = 8;
 }
 
-def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32), Reg32> {
+def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
   let Size = 32;
 }
 
 def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
-                          (add VGPR_32, SReg_32, LDS_DIRECT_CLASS), Reg32> {
+                          (add VGPR_32, SReg_32, LDS_DIRECT_CLASS)> {
   let isAllocatable = 0;
 }
 
 def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64),
                           Reg64> {
   let isAllocatable = 0;
 }
 
 def AV_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
-                          (add AGPR_32, VGPR_32), Reg32> {
+                          (add AGPR_32, VGPR_32)> {
   let isAllocatable = 0;
 }
 
 def AV_64 : RegisterClass<"AMDGPU", [i64, f64, v4f16], 32,
                           (add AReg_64, VReg_64), Reg64> {
   let isAllocatable = 0;
 }