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[GlobalISel][AArch64] Add support for base register + offset register loads
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Authored by paquette on Jul 18 2019, 1:24 PM.

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Summary

Add support for folding G_GEPs into loads of the form

ldr reg, [base, off]

when possible. This can save an add before the load. Currently, this is only supported for loads of 64 bits into 64 bit registers.

Add a new addressing mode function, selectAddrModeRegisterOffset which performs this folding when it is profitable.

Also add a test for addressing modes for G_LOAD.

Diff Detail

Repository
rL LLVM

Event Timeline

paquette created this revision.Jul 18 2019, 1:24 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 18 2019, 1:24 PM
aemerson accepted this revision.Jul 18 2019, 2:12 PM

LGTM.

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
3973 ↗(On Diff #210656)

For future improvements: we can use MachineInstr::mayLoad/mayStore to check the users, even if they've been selected to target instructions.

This revision is now accepted and ready to land.Jul 18 2019, 2:12 PM
This revision was automatically updated to reflect the committed changes.