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Differential D64901

[AMDGPU][NFC] Simplify test file for amdgcn intrinsics
ClosedPublic

Authored by uenoku on Jul 17 2019, 10:55 PM.

Details

Reviewers
nhaehnle
Commits
rG2d654df763c5: [AMDGPU][NFC] Simplify test file for amdgcn intrinsics
rL366781: [AMDGPU][NFC] Simplify test file for amdgcn intrinsics
Summary

Remove unchecked attribute in the call site and use FileCheck String Substitution for convergent check.

Diff Detail

Repository
rL LLVM

Event Timeline

uenoku created this revision.Jul 17 2019, 10:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 17 2019, 10:55 PM
Herald added subscribers: llvm-commits, t-tye, tpr and 6 others. · View Herald Transcript
uenoku retitled this revision from [AMDGPU][NFC] Simplify test file for amdgen intrinsics to [AMDGPU][NFC] Simplify test file for amdgcn intrinsics.Jul 17 2019, 11:02 PM
nhaehnle accepted this revision.Jul 22 2019, 2:26 AM

LGTM

This revision is now accepted and ready to land.Jul 22 2019, 2:26 AM
Closed by commit rL366781: [AMDGPU][NFC] Simplify test file for amdgcn intrinsics (authored by uenoku). · Explain WhyJul 22 2019, 11:48 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
test/
Transforms/
InstCombine/
AMDGPU/
10 lines

Diff 211252

llvm/trunk/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret double 2.000000e+00 ; CHECK-NEXT: ret double 2.000000e+00
; ;
%val = call double @llvm.amdgcn.rcp.f64(double 0.5) nounwind readnone %val = call double @llvm.amdgcn.rcp.f64(double 0.5) nounwind readnone
ret double %val ret double %val
} }
define float @test_constant_fold_rcp_f32_43() nounwind { define float @test_constant_fold_rcp_f32_43() nounwind {
; CHECK-LABEL: @test_constant_fold_rcp_f32_43( ; CHECK-LABEL: @test_constant_fold_rcp_f32_43(
; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) #5 ; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01)
; CHECK-NEXT: ret float [[VAL]] ; CHECK-NEXT: ret float [[VAL]]
; ;
%val = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) nounwind readnone %val = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) nounwind readnone
ret float %val ret float %val
} }
define double @test_constant_fold_rcp_f64_43() nounwind { define double @test_constant_fold_rcp_f64_43() nounwind {
; CHECK-LABEL: @test_constant_fold_rcp_f64_43( ; CHECK-LABEL: @test_constant_fold_rcp_f64_43(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.rcp.f64(double 4.300000e+01) #5 ; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.rcp.f64(double 4.300000e+01)
; CHECK-NEXT: ret double [[VAL]] ; CHECK-NEXT: ret double [[VAL]]
; ;
%val = call double @llvm.amdgcn.rcp.f64(double 4.300000e+01) nounwind readnone %val = call double @llvm.amdgcn.rcp.f64(double 4.300000e+01) nounwind readnone
ret double %val ret double %val
} }
; -------------------------------------------------------------------- ; --------------------------------------------------------------------
; llvm.amdgcn.rsq ; llvm.amdgcn.rsq
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; CHECK-NEXT: ret i64 0 ; CHECK-NEXT: ret i64 0
; ;
%result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 32) %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 32)
ret i64 %result ret i64 %result
} }
define i64 @icmp_constant_inputs_true() { define i64 @icmp_constant_inputs_true() {
; CHECK-LABEL: @icmp_constant_inputs_true( ; CHECK-LABEL: @icmp_constant_inputs_true(
; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata !0) #6 ; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata !0) [[CONVERGENT:#[0-9]*]]
; CHECK-NEXT: ret i64 [[RESULT]] ; CHECK-NEXT: ret i64 [[RESULT]]
; ;
%result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 34) %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 34)
ret i64 %result ret i64 %result
} }
define i64 @icmp_constant_to_rhs_slt(i32 %x) { define i64 @icmp_constant_to_rhs_slt(i32 %x) {
; CHECK-LABEL: @icmp_constant_to_rhs_slt( ; CHECK-LABEL: @icmp_constant_to_rhs_slt(
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; CHECK-NEXT: ret i64 0 ; CHECK-NEXT: ret i64 0
; ;
%result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 1) %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 1)
ret i64 %result ret i64 %result
} }
define i64 @fcmp_constant_inputs_true() { define i64 @fcmp_constant_inputs_true() {
; CHECK-LABEL: @fcmp_constant_inputs_true( ; CHECK-LABEL: @fcmp_constant_inputs_true(
; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata !0) #6 ; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata !0) [[CONVERGENT]]
; CHECK-NEXT: ret i64 [[RESULT]] ; CHECK-NEXT: ret i64 [[RESULT]]
; ;
%result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 4) %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 4)
ret i64 %result ret i64 %result
} }
define i64 @fcmp_constant_to_rhs_olt(float %x) { define i64 @fcmp_constant_to_rhs_olt(float %x) {
; CHECK-LABEL: @fcmp_constant_to_rhs_olt( ; CHECK-LABEL: @fcmp_constant_to_rhs_olt(
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; CHECK-NEXT: store i32 [[TMP0]], i32 addrspace(1)* [[OUT:%.*]], align 4 ; CHECK-NEXT: store i32 [[TMP0]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in1, i32 4, i32 15, i32 15, i1 1) %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in1, i32 4, i32 15, i32 15, i1 1)
store i32 %tmp0, i32 addrspace(1)* %out store i32 %tmp0, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK: attributes #6 = { convergent } ; CHECK: attributes [[CONVERGENT]] = { convergent }