[AMDGPU] Stop special casing flat_scratch for register name

llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp

default: {
           .addImm(Offset);
         FIOp.ChangeToRegister(TmpReg, false, false, true);
       }
     }
   }
 }
 
 StringRef SIRegisterInfo::getRegAsmName(unsigned Reg) const {
-  // FIXME: Rename flat_scr so we don't need to special case this.
-  switch (Reg) {
-  case AMDGPU::FLAT_SCR:
-    return "flat_scratch";
-  case AMDGPU::FLAT_SCR_LO:
-    return "flat_scratch_lo";
-  case AMDGPU::FLAT_SCR_HI:
-    return "flat_scratch_hi";
-  default:
-    break;
-  }
-
   const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
   unsigned Size = getRegSizeInBits(*RC);
   unsigned AltName = AMDGPU::NoRegAltName;
 
   switch (Size) {
   case 32:   AltName = AMDGPU::Reg32; break;
   case 64:   AltName = AMDGPU::Reg64; break;
   case 96:   AltName = AMDGPU::Reg96; break;

llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td

foreach Index = 0-15 in {
   def TTMP#Index#_vi         : SIReg<"ttmp"#Index, !add(112, Index)>;
   def TTMP#Index#_gfx9_gfx10 : SIReg<"ttmp"#Index, !add(108, Index)>;
   def TTMP#Index             : SIReg<"ttmp"#Index, 0>;
 }
 
 multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> {
   def _ci : SIReg<n, ci_e>;
   def _vi : SIReg<n, vi_e>;
-  def "" : SIReg<"", 0>;
+  def "" : SIReg<n, 0>;
 }
 
 class FlatReg <Register lo, Register hi, bits<16> encoding> :
     SIRegisterWithSubRegs<"flat_scratch", [lo, hi]>,
     DwarfRegAlias<lo> {
   let Namespace = "AMDGPU";
   let SubRegIndices = [sub0, sub1];
   let HWEncoding = encoding;