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Differential D64371

[AArch64][GlobalISel] Use TST for comparisons when possible
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Authored by paquette on Jul 8 2019, 3:23 PM.

Details

Reviewers
aemerson
Commits
rG55d19247ef2c: [AArch64][GlobalISel] Use TST for comparisons when possible
rL365404: [AArch64][GlobalISel] Use TST for comparisons when possible
Summary

Porting over the part of emitComparison in AArch64ISelLowering where we use TST to represent a compare.

  • Rename tryOptCMN to tryFoldIntegerCompare, since it now also emits TSTs when possible.
  • Add a utility function for emitting a TST with register operands.
  • Rename opt-fold-cmn.mir to opt-fold-compare.mir, since it now also tests the TST fold as well.

Diff Detail

Repository
rL LLVM

Event Timeline

paquette created this revision.Jul 8 2019, 3:23 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 8 2019, 3:23 PM
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls and 2 others. · View Herald Transcript
aemerson accepted this revision.Jul 8 2019, 3:47 PM

LGTM with comment fix and minor nit.

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
810 ↗(On Diff #208522)

Can just make this default block return false and kill the return after the switch.

This revision is now accepted and ready to land.Jul 8 2019, 3:47 PM
Closed by commit rL365404: [AArch64][GlobalISel] Use TST for comparisons when possible (authored by paquette). · Explain WhyJul 8 2019, 4:01 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AArch64/
143 lines
test/
CodeGen/
AArch64/
GlobalISel/
275 lines
480 lines

Diff 208531

llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Linesprivate:
MachineInstr *emitVectorConcat(Optional<Register> Dst, Register Op1, MachineInstr *emitVectorConcat(Optional<Register> Dst, Register Op1,
Register Op2, Register Op2,
MachineIRBuilder &MIRBuilder) const; MachineIRBuilder &MIRBuilder) const;
MachineInstr *emitIntegerCompare(MachineOperand &LHS, MachineOperand &RHS, MachineInstr *emitIntegerCompare(MachineOperand &LHS, MachineOperand &RHS,
MachineOperand &Predicate, MachineOperand &Predicate,
MachineIRBuilder &MIRBuilder) const; MachineIRBuilder &MIRBuilder) const;
MachineInstr *emitCMN(MachineOperand &LHS, MachineOperand &RHS, MachineInstr *emitCMN(MachineOperand &LHS, MachineOperand &RHS,
MachineIRBuilder &MIRBuilder) const; MachineIRBuilder &MIRBuilder) const;
MachineInstr *emitTST(const Register &LHS, const Register &RHS,
MachineIRBuilder &MIRBuilder) const;
MachineInstr *emitExtractVectorElt(Optional<Register> DstReg, MachineInstr *emitExtractVectorElt(Optional<Register> DstReg,
const RegisterBank &DstRB, LLT ScalarTy, const RegisterBank &DstRB, LLT ScalarTy,
Register VecReg, unsigned LaneIdx, Register VecReg, unsigned LaneIdx,
MachineIRBuilder &MIRBuilder) const; MachineIRBuilder &MIRBuilder) const;
/// Helper function for selecting G_FCONSTANT. If the G_FCONSTANT can be /// Helper function for selecting G_FCONSTANT. If the G_FCONSTANT can be
/// materialized using a FMOV instruction, then update MI and return it. /// materialized using a FMOV instruction, then update MI and return it.
/// Otherwise, do nothing and return a nullptr. /// Otherwise, do nothing and return a nullptr.
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines MachineInstr *findMIFromReg(unsigned Reg, unsigned Opc,
if (!Def || Def->getOpcode() != Opc) if (!Def || Def->getOpcode() != Opc)
return nullptr; return nullptr;
return Def; return Def;
} }
bool tryOptVectorShuffle(MachineInstr &I) const; bool tryOptVectorShuffle(MachineInstr &I) const;
bool tryOptVectorDup(MachineInstr &MI) const; bool tryOptVectorDup(MachineInstr &MI) const;
bool tryOptSelect(MachineInstr &MI) const; bool tryOptSelect(MachineInstr &MI) const;
MachineInstr *tryOptCMN(MachineOperand &LHS, MachineOperand &RHS, MachineInstr *tryFoldIntegerCompare(MachineOperand &LHS, MachineOperand &RHS,
MachineOperand &Predicate, MachineOperand &Predicate,
MachineIRBuilder &MIRBuilder) const; MachineIRBuilder &MIRBuilder) const;
const AArch64TargetMachine &TM; const AArch64TargetMachine &TM;
const AArch64Subtarget &STI; const AArch64Subtarget &STI;
const AArch64InstrInfo &TII; const AArch64InstrInfo &TII;
const AArch64RegisterInfo &TRI; const AArch64RegisterInfo &TRI;
const AArch64RegisterBankInfo &RBI; const AArch64RegisterBankInfo &RBI;
#define GET_GLOBALISEL_PREDICATES_DECL #define GET_GLOBALISEL_PREDICATES_DECL
▲ Show 20 Lines • Show All 580 Lines • ▼ Show 20 Linesstatic unsigned selectFCMPOpc(MachineInstr &I, MachineRegisterInfo &MRI) {
unsigned OpSize = MRI.getType(I.getOperand(2).getReg()).getSizeInBits(); unsigned OpSize = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();
if (OpSize != 32 && OpSize != 64) if (OpSize != 32 && OpSize != 64)
return 0; return 0;
unsigned CmpOpcTbl[2][2] = {{AArch64::FCMPSrr, AArch64::FCMPDrr}, unsigned CmpOpcTbl[2][2] = {{AArch64::FCMPSrr, AArch64::FCMPDrr},
{AArch64::FCMPSri, AArch64::FCMPDri}}; {AArch64::FCMPSri, AArch64::FCMPDri}};
return CmpOpcTbl[ShouldUseImm][OpSize == 64]; return CmpOpcTbl[ShouldUseImm][OpSize == 64];
} }
/// Returns true if \p P is an unsigned integer comparison predicate.
static bool isUnsignedICMPPred(const CmpInst::Predicate P) {
switch (P) {
default:
return false;
case CmpInst::ICMP_UGT:
case CmpInst::ICMP_UGE:
case CmpInst::ICMP_ULT:
case CmpInst::ICMP_ULE:
return true;
}
}
static AArch64CC::CondCode changeICMPPredToAArch64CC(CmpInst::Predicate P) { static AArch64CC::CondCode changeICMPPredToAArch64CC(CmpInst::Predicate P) {
switch (P) { switch (P) {
default: default:
llvm_unreachable("Unknown condition code!"); llvm_unreachable("Unknown condition code!");
case CmpInst::ICMP_NE: case CmpInst::ICMP_NE:
return AArch64CC::NE; return AArch64CC::NE;
case CmpInst::ICMP_EQ: case CmpInst::ICMP_EQ:
return AArch64CC::EQ; return AArch64CC::EQ;
▲ Show 20 Lines • Show All 2,102 Lines • ▼ Show 20 LinesAArch64InstructionSelector::emitCMN(MachineOperand &LHS, MachineOperand &RHS,
} else { } else {
CmpMI.addUse(RHS.getReg()); CmpMI.addUse(RHS.getReg());
} }
constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI); constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
return &*CmpMI; return &*CmpMI;
} }
MachineInstr *
AArch64InstructionSelector::emitTST(const Register &LHS, const Register &RHS,
MachineIRBuilder &MIRBuilder) const {
MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
unsigned RegSize = MRI.getType(LHS).getSizeInBits();
bool Is32Bit = (RegSize == 32);
static const unsigned OpcTable[2][2]{{AArch64::ANDSXrr, AArch64::ANDSXri},
{AArch64::ANDSWrr, AArch64::ANDSWri}};
Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
// We might be able to fold in an immediate into the TST. We need to make sure
// it's a logical immediate though, since ANDS requires that.
auto ValAndVReg = getConstantVRegValWithLookThrough(RHS, MRI);
bool IsImmForm = ValAndVReg.hasValue() &&
AArch64_AM::isLogicalImmediate(ValAndVReg->Value, RegSize);
unsigned Opc = OpcTable[Is32Bit][IsImmForm];
auto TstMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS});
if (IsImmForm)
TstMI.addImm(
AArch64_AM::encodeLogicalImmediate(ValAndVReg->Value, RegSize));
else
TstMI.addUse(RHS);
constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI);
return &*TstMI;
}
MachineInstr *AArch64InstructionSelector::emitIntegerCompare( MachineInstr *AArch64InstructionSelector::emitIntegerCompare(
MachineOperand &LHS, MachineOperand &RHS, MachineOperand &Predicate, MachineOperand &LHS, MachineOperand &RHS, MachineOperand &Predicate,
MachineIRBuilder &MIRBuilder) const { MachineIRBuilder &MIRBuilder) const {
assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!"); assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
// Fold the compare into a CMN if possible. // Fold the compare if possible.
MachineInstr *Cmn = tryOptCMN(LHS, RHS, Predicate, MIRBuilder); MachineInstr *FoldCmp =
if (Cmn) tryFoldIntegerCompare(LHS, RHS, Predicate, MIRBuilder);
return Cmn; if (FoldCmp)
return FoldCmp;
// Can't fold into a CMN. Just emit a normal compare. // Can't fold into a CMN. Just emit a normal compare.
unsigned CmpOpc = 0; unsigned CmpOpc = 0;
Register ZReg; Register ZReg;
LLT CmpTy = MRI.getType(LHS.getReg()); LLT CmpTy = MRI.getType(LHS.getReg());
assert((CmpTy.isScalar() || CmpTy.isPointer()) && assert((CmpTy.isScalar() || CmpTy.isPointer()) &&
"Expected scalar or pointer"); "Expected scalar or pointer");
▲ Show 20 Lines • Show All 225 Lines • ▼ Show 20 Lines auto CSel =
MIB.buildInstr(CSelOpc, {I.getOperand(0).getReg()}, MIB.buildInstr(CSelOpc, {I.getOperand(0).getReg()},
{I.getOperand(2).getReg(), I.getOperand(3).getReg()}) {I.getOperand(2).getReg(), I.getOperand(3).getReg()})
.addImm(CondCode); .addImm(CondCode);
constrainSelectedInstRegOperands(*CSel, TII, TRI, RBI); constrainSelectedInstRegOperands(*CSel, TII, TRI, RBI);
I.eraseFromParent(); I.eraseFromParent();
return true; return true;
} }
MachineInstr * MachineInstr *AArch64InstructionSelector::tryFoldIntegerCompare(
AArch64InstructionSelector::tryOptCMN(MachineOperand &LHS, MachineOperand &RHS, MachineOperand &LHS, MachineOperand &RHS, MachineOperand &Predicate,
MachineOperand &Predicate,
MachineIRBuilder &MIRBuilder) const { MachineIRBuilder &MIRBuilder) const {
assert(LHS.isReg() && RHS.isReg() && Predicate.isPredicate() && assert(LHS.isReg() && RHS.isReg() && Predicate.isPredicate() &&
"Unexpected MachineOperand"); "Unexpected MachineOperand");
MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
// We want to find this sort of thing: // We want to find this sort of thing:
// x = G_SUB 0, y // x = G_SUB 0, y
// G_ICMP z, x // G_ICMP z, x
// //
// In this case, we can fold the G_SUB into the G_ICMP using a CMN instead. // In this case, we can fold the G_SUB into the G_ICMP using a CMN instead.
Show All 38 Lines auto IsCMN = [&](MachineInstr *DefMI, const AArch64CC::CondCode &CC) {
// This can safely be represented as a CMN. // This can safely be represented as a CMN.
return true; return true;
}; };
// Check if the RHS or LHS of the G_ICMP is defined by a SUB // Check if the RHS or LHS of the G_ICMP is defined by a SUB
MachineInstr *LHSDef = FindDef(LHS.getReg()); MachineInstr *LHSDef = FindDef(LHS.getReg());
MachineInstr *RHSDef = FindDef(RHS.getReg()); MachineInstr *RHSDef = FindDef(RHS.getReg());
const AArch64CC::CondCode CC = CmpInst::Predicate P = (CmpInst::Predicate)Predicate.getPredicate();
changeICMPPredToAArch64CC((CmpInst::Predicate)Predicate.getPredicate()); const AArch64CC::CondCode CC = changeICMPPredToAArch64CC(P);
bool DidFold = false;
// Given this:
MachineOperand CMNLHS = LHS;
MachineOperand CMNRHS = RHS;
if (IsCMN(LHSDef, CC)) {
// We're doing this:
//
// Given:
// //
// x = G_SUB 0, y // x = G_SUB 0, y
// G_ICMP x, z // G_ICMP x, z
// //
// Update the G_ICMP: // Produce this:
// //
// G_ICMP y, z // cmn y, z
CMNLHS = LHSDef->getOperand(2); if (IsCMN(LHSDef, CC))
DidFold = true; return emitCMN(LHSDef->getOperand(2), RHS, MIRBuilder);
} else if (IsCMN(RHSDef, CC)) {
// Same idea here, but with the RHS of the compare instead: // Same idea here, but with the RHS of the compare instead:
// //
// Given: // Given this:
// //
// x = G_SUB 0, y // x = G_SUB 0, y
// G_ICMP z, x // G_ICMP z, x
// //
// Update the G_ICMP: // Produce this:
// //
// G_ICMP z, y // cmn z, y
CMNRHS = RHSDef->getOperand(2); if (IsCMN(RHSDef, CC))
DidFold = true; return emitCMN(LHS, RHSDef->getOperand(2), MIRBuilder);
// Given this:
//
// z = G_AND x, y
// G_ICMP z, 0
//
// Produce this if the compare is signed:
//
// tst x, y
if (!isUnsignedICMPPred(P) && LHSDef &&
LHSDef->getOpcode() == TargetOpcode::G_AND) {
// Make sure that the RHS is 0.
auto ValAndVReg = getConstantVRegValWithLookThrough(RHS.getReg(), MRI);
if (!ValAndVReg || ValAndVReg->Value != 0)
return nullptr;
return emitTST(LHSDef->getOperand(1).getReg(),
LHSDef->getOperand(2).getReg(), MIRBuilder);
} }
if (DidFold)
return emitCMN(CMNLHS, CMNRHS, MIRBuilder);
return nullptr; return nullptr;
} }
bool AArch64InstructionSelector::tryOptVectorDup(MachineInstr &I) const { bool AArch64InstructionSelector::tryOptVectorDup(MachineInstr &I) const {
// Try to match a vector splat operation into a dup instruction. // Try to match a vector splat operation into a dup instruction.
// We're looking for this pattern: // We're looking for this pattern:
// %scalar:gpr(s64) = COPY $x0 // %scalar:gpr(s64) = COPY $x0
// %undef:fpr(<2 x s64>) = G_IMPLICIT_DEF // %undef:fpr(<2 x s64>) = G_IMPLICIT_DEF
▲ Show 20 Lines • Show All 703 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/opt-fold-cmn.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify that we can fold G_SUB into G_ICMP when we have a pattern like this:
#
# x = G_SUB 0, y
# G_ICMP intpred(something_safe) z, x
#
# Where "something_safe" is ne or eq.
#
# Tests whose names start with cmn_ should use ADDS for the G_ICMP. Tests whose
# names start with no_cmn should use SUBS.
#
...
---
name: cmn_s32_rhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: cmn_s32_rhs
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_SUB %2, %1
%7:gpr(s32) = G_ICMP intpred(ne), %0(s32), %3
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s32) = G_SELECT %4(s1), %6, %2
$w0 = COPY %5(s32)
RET_ReallyLR implicit $w0
...
---
name: cmn_s32_lhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: cmn_s32_lhs
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_SUB %2, %0
%7:gpr(s32) = G_ICMP intpred(ne), %3(s32), %1
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s32) = G_SELECT %4(s1), %6, %2
$w0 = COPY %5(s32)
RET_ReallyLR implicit $w0
...
---
name: no_cmn_s32_rhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: no_cmn_s32_rhs
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[MOVi32imm]], [[COPY1]], implicit-def $nzcv
; CHECK: $wzr = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 11, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_SUB %2, %1
%7:gpr(s32) = G_ICMP intpred(slt), %0(s32), %3
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s32) = G_SELECT %4(s1), %6, %2
$w0 = COPY %5(s32)
RET_ReallyLR implicit $w0
...
---
name: no_cmn_s32_lhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: no_cmn_s32_lhs
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[MOVi32imm]], [[COPY]], implicit-def $nzcv
; CHECK: $wzr = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 11, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_SUB %2, %0
%7:gpr(s32) = G_ICMP intpred(slt), %3(s32), %1
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s32) = G_SELECT %4(s1), %6, %2
$w0 = COPY %5(s32)
RET_ReallyLR implicit $w0
...
---
name: cmn_s64_rhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: cmn_s64_rhs
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_SUB %2, %1
%7:gpr(s32) = G_ICMP intpred(ne), %0(s64), %3
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s64) = G_SELECT %4(s1), %6, %2
$x0 = COPY %5(s64)
RET_ReallyLR implicit $x0
...
---
name: cmn_s64_lhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: cmn_s64_lhs
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_SUB %2, %0
%7:gpr(s32) = G_ICMP intpred(ne), %3(s64), %1
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s64) = G_SELECT %4(s1), %6, %2
$x0 = COPY %5(s64)
RET_ReallyLR implicit $x0
...
---
name: no_cmn_s64_rhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: no_cmn_s64_rhs
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[MOVi64imm]], [[COPY1]], implicit-def $nzcv
; CHECK: $xzr = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 11, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_SUB %2, %1
%7:gpr(s32) = G_ICMP intpred(slt), %0(s64), %3
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s64) = G_SELECT %4(s1), %6, %2
$x0 = COPY %5(s64)
RET_ReallyLR implicit $x0
...
---
name: no_cmn_s64_lhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: no_cmn_s64_lhs
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[MOVi64imm]], [[COPY]], implicit-def $nzcv
; CHECK: $xzr = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 11, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_SUB %2, %0
%7:gpr(s32) = G_ICMP intpred(slt), %3(s64), %1
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s64) = G_SELECT %4(s1), %6, %2
$x0 = COPY %5(s64)
RET_ReallyLR implicit $x0
...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify folding operations into G_ICMP.
#
# E.g cmn/adds folding:
#
# x = G_SUB 0, y
# G_ICMP intpred(something_safe) z, x
#
# Folds to:
# adds z, y
#
# Where "something_safe" is ne or eq.
#
# ands/tst folding:
#
# z = G_AND x, y
# G_ICMP z, 0
#
# Folds to:
#
# tst x, y
#
# When we have signed comparisons.
#
# Tests whose names start with cmn_ should use ADDS for the G_ICMP. Tests whose
# names start with no_cmn should use SUBS. Similarly, tests whose names start
# with TST should use ANDS for the G_ICMP.
#
...
---
name: cmn_s32_rhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: cmn_s32_rhs
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_SUB %2, %1
%7:gpr(s32) = G_ICMP intpred(ne), %0(s32), %3
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s32) = G_SELECT %4(s1), %6, %2
$w0 = COPY %5(s32)
RET_ReallyLR implicit $w0
...
---
name: cmn_s32_lhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: cmn_s32_lhs
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 1, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_SUB %2, %0
%7:gpr(s32) = G_ICMP intpred(ne), %3(s32), %1
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s32) = G_SELECT %4(s1), %6, %2
$w0 = COPY %5(s32)
RET_ReallyLR implicit $w0
...
---
name: no_cmn_s32_rhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: no_cmn_s32_rhs
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[MOVi32imm]], [[COPY1]], implicit-def $nzcv
; CHECK: $wzr = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 11, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_SUB %2, %1
%7:gpr(s32) = G_ICMP intpred(slt), %0(s32), %3
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s32) = G_SELECT %4(s1), %6, %2
$w0 = COPY %5(s32)
RET_ReallyLR implicit $w0
...
---
name: no_cmn_s32_lhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: no_cmn_s32_lhs
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[MOVi32imm]], [[COPY]], implicit-def $nzcv
; CHECK: $wzr = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 11, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_SUB %2, %0
%7:gpr(s32) = G_ICMP intpred(slt), %3(s32), %1
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s32) = G_SELECT %4(s1), %6, %2
$w0 = COPY %5(s32)
RET_ReallyLR implicit $w0
...
---
name: cmn_s64_rhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: cmn_s64_rhs
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_SUB %2, %1
%7:gpr(s32) = G_ICMP intpred(ne), %0(s64), %3
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s64) = G_SELECT %4(s1), %6, %2
$x0 = COPY %5(s64)
RET_ReallyLR implicit $x0
...
---
name: cmn_s64_lhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: cmn_s64_lhs
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 1, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_SUB %2, %0
%7:gpr(s32) = G_ICMP intpred(ne), %3(s64), %1
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s64) = G_SELECT %4(s1), %6, %2
$x0 = COPY %5(s64)
RET_ReallyLR implicit $x0
...
---
name: no_cmn_s64_rhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: no_cmn_s64_rhs
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[MOVi64imm]], [[COPY1]], implicit-def $nzcv
; CHECK: $xzr = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 11, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_SUB %2, %1
%7:gpr(s32) = G_ICMP intpred(slt), %0(s64), %3
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s64) = G_SELECT %4(s1), %6, %2
$x0 = COPY %5(s64)
RET_ReallyLR implicit $x0
...
---
name: no_cmn_s64_lhs
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: no_cmn_s64_lhs
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[MOVi64imm]], [[COPY]], implicit-def $nzcv
; CHECK: $xzr = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 11, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_SUB %2, %0
%7:gpr(s32) = G_ICMP intpred(slt), %3(s64), %1
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s64) = G_SELECT %4(s1), %6, %2
$x0 = COPY %5(s64)
RET_ReallyLR implicit $x0
...
---
name: tst_s32
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: tst_s32
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: $wzr = ANDSWrr [[MOVi32imm]], [[COPY]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 0, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_AND %2, %1
%8:gpr(s32) = G_CONSTANT i32 0
%7:gpr(s32) = G_ICMP intpred(eq), %3(s32), %8
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s32) = G_SELECT %4(s1), %6, %2
$w0 = COPY %5(s32)
RET_ReallyLR implicit $w0
...
---
name: tst_s64
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: tst_s64
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 0
; CHECK: [[MOVi64imm1:%[0-9]+]]:gpr64 = MOVi64imm 1
; CHECK: $xzr = ANDSXrr [[MOVi64imm]], [[COPY]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[MOVi64imm1]], [[MOVi64imm]], 0, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_AND %2, %1
%8:gpr(s64) = G_CONSTANT i64 0
%7:gpr(s32) = G_ICMP intpred(eq), %3(s64), %8
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s64) = G_SELECT %4(s1), %6, %2
$x0 = COPY %5(s64)
RET_ReallyLR implicit $x0
...
---
name: no_tst_unsigned_compare
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: no_tst_unsigned_compare
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[MOVi32imm]], [[COPY]]
; CHECK: $wzr = SUBSWri [[ANDWrr]], 0, 0, implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 8, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_AND %2, %1
%8:gpr(s32) = G_CONSTANT i32 0
%7:gpr(s32) = G_ICMP intpred(ugt), %3(s32), %8
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s32) = G_SELECT %4(s1), %6, %2
$w0 = COPY %5(s32)
RET_ReallyLR implicit $w0
...
---
name: no_tst_nonzero
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: no_tst_nonzero
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[MOVi32imm]], [[COPY]]
; CHECK: $wzr = SUBSWri [[ANDWrr]], 42, 0, implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm1]], [[MOVi32imm]], 8, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_AND %2, %1
%8:gpr(s32) = G_CONSTANT i32 42
%7:gpr(s32) = G_ICMP intpred(ugt), %3(s32), %8
%4:gpr(s1) = G_TRUNC %7(s32)
%5:gpr(s32) = G_SELECT %4(s1), %6, %2
$w0 = COPY %5(s32)
RET_ReallyLR implicit $w0
...
---
name: imm_tst
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: imm_tst
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: $wzr = ANDSWri [[COPY]], 1, implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK: $w0 = COPY [[CSINCWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0
%3:gpr(s32) = G_CONSTANT i32 1
; This can be represented as a logical immediate, so we can pull it into
; the ANDS. We should get ANDSWri.
%4:gpr(s32) = G_CONSTANT i32 3
%5:gpr(s32) = G_AND %1, %4
%6:gpr(s32) = G_ICMP intpred(eq), %5(s32), %2
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: no_imm_tst_not_logical_imm
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: no_imm_tst_not_logical_imm
; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -1
; CHECK: $wzr = ANDSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK: $w0 = COPY [[CSINCWr]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0
%3:gpr(s32) = G_CONSTANT i32 1
; This immediate can't be represented as a logical immediate. We shouldn't
; select ANDSWri.
%4:gpr(s32) = G_CONSTANT i32 -1
%5:gpr(s32) = G_AND %1, %4
%6:gpr(s32) = G_ICMP intpred(eq), %5(s32), %2
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp