This is an archive of the discontinued LLVM Phabricator instance.

Differential D63568

hwasan: Shrink outlined checks by 1 instruction.
ClosedPublic

Authored by pcc on Jun 19 2019, 12:42 PM.

Details

Reviewers
eugenis
Commits
rG2742eeb78e3e: hwasan: Shrink outlined checks by 1 instruction.
rL363874: hwasan: Shrink outlined checks by 1 instruction.
Summary

Turns out that we can save an instruction by folding the right shift into
the compare.

Diff Detail

Repository
rL LLVM

Event Timeline

pcc created this revision.Jun 19 2019, 12:42 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 19 2019, 12:42 PM
Herald added subscribers: hiraditya, javed.absar. · View Herald Transcript
Harbormaster completed remote builds in B33640: Diff 205657.Jun 19 2019, 12:44 PM
eugenis accepted this revision.Jun 19 2019, 1:28 PM

LGTM

This revision is now accepted and ready to land.Jun 19 2019, 1:28 PM
Closed by commit rL363874: hwasan: Shrink outlined checks by 1 instruction. (authored by pcc). · Explain WhyJun 19 2019, 1:36 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AArch64/
19 lines
test/
CodeGen/
AArch64/
6 lines

Diff 205662

llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp

Show First 20 Lines • Show All 291 Lines • ▼ Show 20 Lines OutStreamer->EmitInstruction(MCInstBuilder(AArch64::UBFMXri)
*STI); *STI);
OutStreamer->EmitInstruction(MCInstBuilder(AArch64::LDRBBroX) OutStreamer->EmitInstruction(MCInstBuilder(AArch64::LDRBBroX)
.addReg(AArch64::W16) .addReg(AArch64::W16)
.addReg(AArch64::X9) .addReg(AArch64::X9)
.addReg(AArch64::X16) .addReg(AArch64::X16)
.addImm(0) .addImm(0)
.addImm(0), .addImm(0),
*STI); *STI);
OutStreamer->EmitInstruction(MCInstBuilder(AArch64::UBFMXri) OutStreamer->EmitInstruction(
.addReg(AArch64::X17) MCInstBuilder(AArch64::SUBSXrs)
.addReg(AArch64::XZR)
.addReg(AArch64::X16)
.addReg(Reg) .addReg(Reg)
.addImm(56) .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
.addImm(63),
*STI);
OutStreamer->EmitInstruction(MCInstBuilder(AArch64::SUBSWrs)
.addReg(AArch64::WZR)
.addReg(AArch64::W16)
.addReg(AArch64::W17)
.addImm(0),
*STI); *STI);
MCSymbol *HandleMismatchSym = OutContext.createTempSymbol(); MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
OutStreamer->EmitInstruction( OutStreamer->EmitInstruction(
MCInstBuilder(AArch64::Bcc) MCInstBuilder(AArch64::Bcc)
.addImm(AArch64CC::NE) .addImm(AArch64CC::NE)
.addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)), .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
*STI); *STI);
OutStreamer->EmitInstruction( OutStreamer->EmitInstruction(
MCInstBuilder(AArch64::RET).addReg(AArch64::LR), *STI); MCInstBuilder(AArch64::RET).addReg(AArch64::LR), *STI);
▲ Show 20 Lines • Show All 817 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/hwasan-check-memaccess.ll

Show All 32 Lines
; CHECK: .section .text.hot,"axG",@progbits,__hwasan_check_x0_456,comdat ; CHECK: .section .text.hot,"axG",@progbits,__hwasan_check_x0_456,comdat
; CHECK-NEXT: .type __hwasan_check_x0_456,@function ; CHECK-NEXT: .type __hwasan_check_x0_456,@function
; CHECK-NEXT: .weak __hwasan_check_x0_456 ; CHECK-NEXT: .weak __hwasan_check_x0_456
; CHECK-NEXT: .hidden __hwasan_check_x0_456 ; CHECK-NEXT: .hidden __hwasan_check_x0_456
; CHECK-NEXT: __hwasan_check_x0_456: ; CHECK-NEXT: __hwasan_check_x0_456:
; CHECK-NEXT: ubfx x16, x0, #4, #52 ; CHECK-NEXT: ubfx x16, x0, #4, #52
; CHECK-NEXT: ldrb w16, [x9, x16] ; CHECK-NEXT: ldrb w16, [x9, x16]
; CHECK-NEXT: lsr x17, x0, #56 ; CHECK-NEXT: cmp x16, x0, lsr #56
; CHECK-NEXT: cmp w16, w17
; CHECK-NEXT: b.ne .Ltmp0 ; CHECK-NEXT: b.ne .Ltmp0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .Ltmp0: ; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: stp x0, x1, [sp, #-256]! ; CHECK-NEXT: stp x0, x1, [sp, #-256]!
; CHECK-NEXT: stp x29, x30, [sp, #232] ; CHECK-NEXT: stp x29, x30, [sp, #232]
; CHECK-NEXT: mov x1, #456 ; CHECK-NEXT: mov x1, #456
; CHECK-NEXT: adrp x16, :got:__hwasan_tag_mismatch ; CHECK-NEXT: adrp x16, :got:__hwasan_tag_mismatch
; CHECK-NEXT: ldr x16, [x16, :got_lo12:__hwasan_tag_mismatch] ; CHECK-NEXT: ldr x16, [x16, :got_lo12:__hwasan_tag_mismatch]
; CHECK-NEXT: br x16 ; CHECK-NEXT: br x16
; CHECK: .section .text.hot,"axG",@progbits,__hwasan_check_x1_123,comdat ; CHECK: .section .text.hot,"axG",@progbits,__hwasan_check_x1_123,comdat
; CHECK-NEXT: .type __hwasan_check_x1_123,@function ; CHECK-NEXT: .type __hwasan_check_x1_123,@function
; CHECK-NEXT: .weak __hwasan_check_x1_123 ; CHECK-NEXT: .weak __hwasan_check_x1_123
; CHECK-NEXT: .hidden __hwasan_check_x1_123 ; CHECK-NEXT: .hidden __hwasan_check_x1_123
; CHECK-NEXT: __hwasan_check_x1_123: ; CHECK-NEXT: __hwasan_check_x1_123:
; CHECK-NEXT: ubfx x16, x1, #4, #52 ; CHECK-NEXT: ubfx x16, x1, #4, #52
; CHECK-NEXT: ldrb w16, [x9, x16] ; CHECK-NEXT: ldrb w16, [x9, x16]
; CHECK-NEXT: lsr x17, x1, #56 ; CHECK-NEXT: cmp x16, x1, lsr #56
; CHECK-NEXT: cmp w16, w17
; CHECK-NEXT: b.ne .Ltmp1 ; CHECK-NEXT: b.ne .Ltmp1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .Ltmp1: ; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: stp x0, x1, [sp, #-256]! ; CHECK-NEXT: stp x0, x1, [sp, #-256]!
; CHECK-NEXT: stp x29, x30, [sp, #232] ; CHECK-NEXT: stp x29, x30, [sp, #232]
; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: mov x1, #123 ; CHECK-NEXT: mov x1, #123
; CHECK-NEXT: adrp x16, :got:__hwasan_tag_mismatch ; CHECK-NEXT: adrp x16, :got:__hwasan_tag_mismatch
; CHECK-NEXT: ldr x16, [x16, :got_lo12:__hwasan_tag_mismatch] ; CHECK-NEXT: ldr x16, [x16, :got_lo12:__hwasan_tag_mismatch]
; CHECK-NEXT: br x16 ; CHECK-NEXT: br x16