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Differential D63200

gn build: Simplify Target build files
ClosedPublic

Authored by thakis on Jun 12 2019, 7:03 AM.

Details

Reviewers
phosek
Commits
rG3819e68b9c9d: gn build: Simplify Target build files
rL363436: gn build: Simplify Target build files
Summary

Now that the cycle between MCTargetDesc and TargetInfo is gone
(see revisions 360709 360718 360722 360724 360726 360731 360733 360735 360736),
remove the dependency from TargetInfo on MCTargetDesc:tablegen. In most
targets, this makes MCTargetDesc:tablegen have just a single use, so
inline it there.

For AArch64, ARM, and RISCV there's still a similar cycle between
MCTargetDesc and Utils, so the MCTargetDesc:tablegen indirection is
still needed there.

Diff Detail

Repository
rL LLVM

Event Timeline

thakis created this revision.Jun 12 2019, 7:03 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 12 2019, 7:03 AM
Herald added subscribers: jsji, jocewei, PkmX and 23 others. · View Herald Transcript
thakis added a comment.Jun 13 2019, 11:24 AM

phosek: Ping :)

thakis added a comment.Jun 14 2019, 5:56 AM

phosek: Ping :|

phosek accepted this revision.Jun 14 2019, 10:41 AM

LGTM

This revision is now accepted and ready to land.Jun 14 2019, 10:41 AM
Closed by commit rL363436: gn build: Simplify Target build files (authored by nico). · Explain WhyJun 14 2019, 10:55 AM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: jrtc27. · View Herald TranscriptJun 14 2019, 10:55 AM

Revision Contents

PathSize
llvm/
trunk/
utils/
gn/
secondary/
llvm/
lib/
Target/
AArch64/
MCTargetDesc/
1 line
TargetInfo/
4 lines
Utils/
3 lines
ARM/
MCTargetDesc/
2 lines
TargetInfo/
4 lines
Utils/
3 lines
BPF/
MCTargetDesc/
27 lines
TargetInfo/
4 lines
Hexagon/
MCTargetDesc/
24 lines
TargetInfo/
5 lines
Lanai/
MCTargetDesc/
27 lines
TargetInfo/
1 line
PowerPC/
MCTargetDesc/
28 lines
TargetInfo/
4 lines
RISCV/
Utils/
3 lines
Sparc/
MCTargetDesc/
27 lines
TargetInfo/
2 lines
WebAssembly/
MCTargetDesc/
28 lines
TargetInfo/
4 lines
X86/
MCTargetDesc/
27 lines
TargetInfo/
4 lines

Diff 204814

llvm/trunk/utils/gn/secondary/llvm/lib/Target/AArch64/MCTargetDesc/BUILD.gn

Show All 39 Lines
} }
# This should contain tablegen targets generating .inc files included # This should contain tablegen targets generating .inc files included
# by other targets. .inc files only used by .cpp files in this directory # by other targets. .inc files only used by .cpp files in this directory
# should be in deps on the static_library instead. # should be in deps on the static_library instead.
group("tablegen") { group("tablegen") {
visibility = [ visibility = [
":MCTargetDesc", ":MCTargetDesc",
"../TargetInfo",
"../Utils", "../Utils",
] ]
public_deps = [ public_deps = [
":AArch64GenInstrInfo", ":AArch64GenInstrInfo",
":AArch64GenRegisterInfo", ":AArch64GenRegisterInfo",
":AArch64GenSubtargetInfo", ":AArch64GenSubtargetInfo",
] ]
} }
Show All 31 Lines

llvm/trunk/utils/gn/secondary/llvm/lib/Target/AArch64/TargetInfo/BUILD.gn

static_library("TargetInfo") { static_library("TargetInfo") {
output_name = "LLVMAArch64Info" output_name = "LLVMAArch64Info"
deps = [ deps = [
"//llvm/lib/Support", "//llvm/lib/Support",
# MCTargetDesc depends on TargetInfo, so we can't depend on the full
# MCTargetDesc target here: it would form a cycle.
"//llvm/lib/Target/AArch64/MCTargetDesc:tablegen",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
sources = [ sources = [
"AArch64TargetInfo.cpp", "AArch64TargetInfo.cpp",
] ]
} }

llvm/trunk/utils/gn/secondary/llvm/lib/Target/AArch64/Utils/BUILD.gn

import("//llvm/utils/TableGen/tablegen.gni") import("//llvm/utils/TableGen/tablegen.gni")
tablegen("AArch64GenSystemOperands") { tablegen("AArch64GenSystemOperands") {
visibility = [ ":Utils" ] visibility = [ ":Utils" ]
args = [ "-gen-searchable-tables" ] args = [ "-gen-searchable-tables" ]
td_file = "../AArch64.td" td_file = "../AArch64.td"
} }
static_library("Utils") { static_library("Utils") {
output_name = "LLVMAArch64Utils" output_name = "LLVMAArch64Utils"
public_deps = [ public_deps = [
":AArch64GenSystemOperands", ":AArch64GenSystemOperands",
] ]
deps = [ deps = [
"//llvm/lib/Support", "//llvm/lib/Support",
# MCTargetDesc depends on Utils, so we can't depend on the full
# MCTargetDesc target here: it would form a cycle.
"//llvm/lib/Target/AArch64/MCTargetDesc:tablegen", "//llvm/lib/Target/AArch64/MCTargetDesc:tablegen",
] ]
# AArch64BaseInfo.h includes a header from MCTargetDesc :-/ # AArch64BaseInfo.h includes a header from MCTargetDesc :-/
include_dirs = [ ".." ] include_dirs = [ ".." ]
sources = [ sources = [
"AArch64BaseInfo.cpp", "AArch64BaseInfo.cpp",
] ]
} }

llvm/trunk/utils/gn/secondary/llvm/lib/Target/ARM/MCTargetDesc/BUILD.gn

Show All 30 Lines
} }
# This should contain tablegen targets generating .inc files included # This should contain tablegen targets generating .inc files included
# by other targets. .inc files only used by .cpp files in this directory # by other targets. .inc files only used by .cpp files in this directory
# should be in deps on the static_library instead. # should be in deps on the static_library instead.
group("tablegen") { group("tablegen") {
visibility = [ visibility = [
":MCTargetDesc", ":MCTargetDesc",
"../TargetInfo",
"../Utils", "../Utils",
] ]
public_deps = [ public_deps = [
":ARMGenInstrInfo", ":ARMGenInstrInfo",
":ARMGenRegisterInfo", ":ARMGenRegisterInfo",
":ARMGenSubtargetInfo", ":ARMGenSubtargetInfo",
] ]
} }
static_library("MCTargetDesc") { static_library("MCTargetDesc") {
output_name = "LLVMARMDesc" output_name = "LLVMARMDesc"
public_deps = [ public_deps = [
":tablegen", ":tablegen",
] ]
deps = [ deps = [
":ARMGenAsmWriter", ":ARMGenAsmWriter",
":ARMGenMCCodeEmitter", ":ARMGenMCCodeEmitter",
Show All 24 Lines

llvm/trunk/utils/gn/secondary/llvm/lib/Target/ARM/TargetInfo/BUILD.gn

static_library("TargetInfo") { static_library("TargetInfo") {
output_name = "LLVMARMInfo" output_name = "LLVMARMInfo"
deps = [ deps = [
"//llvm/lib/Support", "//llvm/lib/Support",
# MCTargetDesc depends on TargetInfo, so we can't depend on the full
# MCTargetDesc target here: it would form a cycle.
"//llvm/lib/Target/ARM/MCTargetDesc:tablegen",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
sources = [ sources = [
"ARMTargetInfo.cpp", "ARMTargetInfo.cpp",
] ]
} }

llvm/trunk/utils/gn/secondary/llvm/lib/Target/ARM/Utils/BUILD.gn

import("//llvm/utils/TableGen/tablegen.gni") import("//llvm/utils/TableGen/tablegen.gni")
tablegen("ARMGenSystemRegister") { tablegen("ARMGenSystemRegister") {
visibility = [ ":Utils" ] visibility = [ ":Utils" ]
args = [ "-gen-searchable-tables" ] args = [ "-gen-searchable-tables" ]
td_file = "../ARM.td" td_file = "../ARM.td"
} }
static_library("Utils") { static_library("Utils") {
output_name = "LLVMARMUtils" output_name = "LLVMARMUtils"
public_deps = [ public_deps = [
":ARMGenSystemRegister", ":ARMGenSystemRegister",
] ]
deps = [ deps = [
"//llvm/lib/Support", "//llvm/lib/Support",
# MCTargetDesc depends on Utils, so we can't depend on the full
# MCTargetDesc target here: it would form a cycle.
"//llvm/lib/Target/ARM/MCTargetDesc:tablegen", "//llvm/lib/Target/ARM/MCTargetDesc:tablegen",
] ]
# ARMBaseInfo.h includes a header from MCTargetDesc, # ARMBaseInfo.h includes a header from MCTargetDesc,
# https://reviews.llvm.org/D35209#1075113 :-/ # https://reviews.llvm.org/D35209#1075113 :-/
include_dirs = [ ".." ] include_dirs = [ ".." ]
sources = [ sources = [
"ARMBaseInfo.cpp", "ARMBaseInfo.cpp",
] ]
} }

llvm/trunk/utils/gn/secondary/llvm/lib/Target/BPF/MCTargetDesc/BUILD.gn

import("//llvm/utils/TableGen/tablegen.gni") import("//llvm/utils/TableGen/tablegen.gni")
tablegen("BPFGenAsmWriter") { tablegen("BPFGenAsmWriter") {
visibility = [ ":MCTargetDesc" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-asm-writer" ] args = [ "-gen-asm-writer" ]
td_file = "../BPF.td" td_file = "../BPF.td"
} }
tablegen("BPFGenInstrInfo") { tablegen("BPFGenInstrInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-instr-info" ] args = [ "-gen-instr-info" ]
td_file = "../BPF.td" td_file = "../BPF.td"
} }
tablegen("BPFGenMCCodeEmitter") { tablegen("BPFGenMCCodeEmitter") {
visibility = [ ":MCTargetDesc" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-emitter" ] args = [ "-gen-emitter" ]
td_file = "../BPF.td" td_file = "../BPF.td"
} }
tablegen("BPFGenRegisterInfo") { tablegen("BPFGenRegisterInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-register-info" ] args = [ "-gen-register-info" ]
td_file = "../BPF.td" td_file = "../BPF.td"
} }
tablegen("BPFGenSubtargetInfo") { tablegen("BPFGenSubtargetInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-subtarget" ] args = [ "-gen-subtarget" ]
td_file = "../BPF.td" td_file = "../BPF.td"
} }
static_library("MCTargetDesc") {
output_name = "LLVMBPFDesc"
# This should contain tablegen targets generating .inc files included # This should contain tablegen targets generating .inc files included
# by other targets. .inc files only used by .cpp files in this directory # by other targets. .inc files only used by .cpp files in this directory
# should be in deps on the static_library instead. # should be in deps instead.
group("tablegen") {
visibility = [
":MCTargetDesc",
"../TargetInfo",
]
public_deps = [ public_deps = [
":BPFGenInstrInfo", ":BPFGenInstrInfo",
":BPFGenRegisterInfo", ":BPFGenRegisterInfo",
":BPFGenSubtargetInfo", ":BPFGenSubtargetInfo",
] ]
}
static_library("MCTargetDesc") {
output_name = "LLVMBPFDesc"
public_deps = [
":tablegen",
]
deps = [ deps = [
":BPFGenAsmWriter", ":BPFGenAsmWriter",
":BPFGenMCCodeEmitter", ":BPFGenMCCodeEmitter",
"//llvm/lib/MC", "//llvm/lib/MC",
"//llvm/lib/MC/MCDisassembler", "//llvm/lib/MC/MCDisassembler",
"//llvm/lib/Support", "//llvm/lib/Support",
"//llvm/lib/Target/BPF/TargetInfo", "//llvm/lib/Target/BPF/TargetInfo",
] ]
Show All 9 Lines

llvm/trunk/utils/gn/secondary/llvm/lib/Target/BPF/TargetInfo/BUILD.gn

static_library("TargetInfo") { static_library("TargetInfo") {
output_name = "LLVMBPFInfo" output_name = "LLVMBPFInfo"
deps = [ deps = [
"//llvm/lib/Support", "//llvm/lib/Support",
# MCTargetDesc depends on TargetInfo, so we can't depend on the full
# MCTargetDesc target here: it would form a cycle.
"//llvm/lib/Target/BPF/MCTargetDesc:tablegen",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
sources = [ sources = [
"BPFTargetInfo.cpp", "BPFTargetInfo.cpp",
] ]
} }

llvm/trunk/utils/gn/secondary/llvm/lib/Target/Hexagon/MCTargetDesc/BUILD.gn

import("//llvm/utils/TableGen/tablegen.gni") import("//llvm/utils/TableGen/tablegen.gni")
tablegen("HexagonGenAsmWriter") { tablegen("HexagonGenAsmWriter") {
visibility = [ ":MCTargetDesc" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-asm-writer" ] args = [ "-gen-asm-writer" ]
td_file = "../Hexagon.td" td_file = "../Hexagon.td"
} }
tablegen("HexagonGenInstrInfo") { tablegen("HexagonGenInstrInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-instr-info" ] args = [ "-gen-instr-info" ]
td_file = "../Hexagon.td" td_file = "../Hexagon.td"
} }
tablegen("HexagonGenMCCodeEmitter") { tablegen("HexagonGenMCCodeEmitter") {
visibility = [ ":MCTargetDesc" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-emitter" ] args = [ "-gen-emitter" ]
td_file = "../Hexagon.td" td_file = "../Hexagon.td"
} }
tablegen("HexagonGenRegisterInfo") { tablegen("HexagonGenRegisterInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-register-info" ] args = [ "-gen-register-info" ]
td_file = "../Hexagon.td" td_file = "../Hexagon.td"
} }
tablegen("HexagonGenSubtargetInfo") { tablegen("HexagonGenSubtargetInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-subtarget" ] args = [ "-gen-subtarget" ]
td_file = "../Hexagon.td" td_file = "../Hexagon.td"
} }
group("tablegen") { static_library("MCTargetDesc") {
visibility = [ output_name = "LLVMHexagonDesc"
":MCTargetDesc",
"../TargetInfo", # This should contain tablegen targets generating .inc files included
] # by other targets. .inc files only used by .cpp files in this directory
# should be in deps instead.
public_deps = [ public_deps = [
":HexagonGenInstrInfo", ":HexagonGenInstrInfo",
":HexagonGenRegisterInfo", ":HexagonGenRegisterInfo",
":HexagonGenSubtargetInfo", ":HexagonGenSubtargetInfo",
] ]
}
static_library("MCTargetDesc") {
output_name = "LLVMHexagonDesc"
public_deps = [
":tablegen",
]
deps = [ deps = [
":HexagonGenAsmWriter", ":HexagonGenAsmWriter",
":HexagonGenMCCodeEmitter", ":HexagonGenMCCodeEmitter",
"//llvm/lib/MC", "//llvm/lib/MC",
"//llvm/lib/Support", "//llvm/lib/Support",
"//llvm/lib/Target/Hexagon/TargetInfo", "//llvm/lib/Target/Hexagon/TargetInfo",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
Show All 17 Lines

llvm/trunk/utils/gn/secondary/llvm/lib/Target/Hexagon/TargetInfo/BUILD.gn

static_library("TargetInfo") { static_library("TargetInfo") {
output_name = "LLVMHexagonInfo" output_name = "LLVMHexagonInfo"
deps = [ deps = [
"//llvm/lib/IR",
"//llvm/lib/Support", "//llvm/lib/Support",
# MCTargetDesc depends on TargetInfo, so we can't depend on the full
# MCTargetDesc target here: it would form a cycle.
"//llvm/lib/Target/Hexagon/MCTargetDesc:tablegen",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
sources = [ sources = [
"HexagonTargetInfo.cpp", "HexagonTargetInfo.cpp",
] ]
} }

llvm/trunk/utils/gn/secondary/llvm/lib/Target/Lanai/MCTargetDesc/BUILD.gn

import("//llvm/utils/TableGen/tablegen.gni") import("//llvm/utils/TableGen/tablegen.gni")
tablegen("LanaiGenAsmWriter") { tablegen("LanaiGenAsmWriter") {
visibility = [ ":MCTargetDesc" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-asm-writer" ] args = [ "-gen-asm-writer" ]
td_file = "../Lanai.td" td_file = "../Lanai.td"
} }
tablegen("LanaiGenInstrInfo") { tablegen("LanaiGenInstrInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-instr-info" ] args = [ "-gen-instr-info" ]
td_file = "../Lanai.td" td_file = "../Lanai.td"
} }
tablegen("LanaiGenMCCodeEmitter") { tablegen("LanaiGenMCCodeEmitter") {
visibility = [ ":MCTargetDesc" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-emitter" ] args = [ "-gen-emitter" ]
td_file = "../Lanai.td" td_file = "../Lanai.td"
} }
tablegen("LanaiGenRegisterInfo") { tablegen("LanaiGenRegisterInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-register-info" ] args = [ "-gen-register-info" ]
td_file = "../Lanai.td" td_file = "../Lanai.td"
} }
tablegen("LanaiGenSubtargetInfo") { tablegen("LanaiGenSubtargetInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-subtarget" ] args = [ "-gen-subtarget" ]
td_file = "../Lanai.td" td_file = "../Lanai.td"
} }
static_library("MCTargetDesc") {
output_name = "LLVMLanaiDesc"
# This should contain tablegen targets generating .inc files included # This should contain tablegen targets generating .inc files included
# by other targets. .inc files only used by .cpp files in this directory # by other targets. .inc files only used by .cpp files in this directory
# should be in deps on the static_library instead. # should be in deps instead.
group("tablegen") {
visibility = [
":MCTargetDesc",
"../TargetInfo",
]
public_deps = [ public_deps = [
":LanaiGenInstrInfo", ":LanaiGenInstrInfo",
":LanaiGenRegisterInfo", ":LanaiGenRegisterInfo",
":LanaiGenSubtargetInfo", ":LanaiGenSubtargetInfo",
] ]
}
static_library("MCTargetDesc") {
output_name = "LLVMLanaiDesc"
public_deps = [
":tablegen",
]
deps = [ deps = [
":LanaiGenAsmWriter", ":LanaiGenAsmWriter",
":LanaiGenMCCodeEmitter", ":LanaiGenMCCodeEmitter",
"//llvm/lib/MC", "//llvm/lib/MC",
"//llvm/lib/Support", "//llvm/lib/Support",
"//llvm/lib/Target/Lanai/TargetInfo", "//llvm/lib/Target/Lanai/TargetInfo",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
Show All 10 Lines

llvm/trunk/utils/gn/secondary/llvm/lib/Target/Lanai/TargetInfo/BUILD.gn

static_library("TargetInfo") { static_library("TargetInfo") {
output_name = "LLVMLanaiInfo" output_name = "LLVMLanaiInfo"
deps = [ deps = [
"//llvm/lib/IR",
"//llvm/lib/Support", "//llvm/lib/Support",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
sources = [ sources = [
"LanaiTargetInfo.cpp", "LanaiTargetInfo.cpp",
] ]
} }

llvm/trunk/utils/gn/secondary/llvm/lib/Target/PowerPC/MCTargetDesc/BUILD.gn

import("//llvm/utils/TableGen/tablegen.gni") import("//llvm/utils/TableGen/tablegen.gni")
tablegen("PPCGenAsmWriter") { tablegen("PPCGenAsmWriter") {
visibility = [ ":MCTargetDesc" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-asm-writer" ] args = [ "-gen-asm-writer" ]
td_file = "../PPC.td" td_file = "../PPC.td"
} }
tablegen("PPCGenInstrInfo") { tablegen("PPCGenInstrInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-instr-info" ] args = [ "-gen-instr-info" ]
td_file = "../PPC.td" td_file = "../PPC.td"
} }
tablegen("PPCGenMCCodeEmitter") { tablegen("PPCGenMCCodeEmitter") {
visibility = [ ":MCTargetDesc" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-emitter" ] args = [ "-gen-emitter" ]
td_file = "../PPC.td" td_file = "../PPC.td"
} }
tablegen("PPCGenRegisterInfo") { tablegen("PPCGenRegisterInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-register-info" ] args = [ "-gen-register-info" ]
td_file = "../PPC.td" td_file = "../PPC.td"
} }
tablegen("PPCGenSubtargetInfo") { tablegen("PPCGenSubtargetInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-subtarget" ] args = [ "-gen-subtarget" ]
td_file = "../PPC.td" td_file = "../PPC.td"
} }
static_library("MCTargetDesc") {
output_name = "LLVMPowerPCDesc"
# This should contain tablegen targets generating .inc files included # This should contain tablegen targets generating .inc files included
# by other targets. .inc files only used by .cpp files in this directory # by other targets. .inc files only used by .cpp files in this directory
# should be in deps on the static_library instead. # should be in deps instead.
group("tablegen") {
visibility = [
":MCTargetDesc",
"../InstPrinter",
"../TargetInfo",
]
public_deps = [ public_deps = [
":PPCGenInstrInfo", ":PPCGenInstrInfo",
":PPCGenRegisterInfo", ":PPCGenRegisterInfo",
":PPCGenSubtargetInfo", ":PPCGenSubtargetInfo",
] ]
}
static_library("MCTargetDesc") {
output_name = "LLVMPowerPCDesc"
public_deps = [
":tablegen",
]
deps = [ deps = [
":PPCGenAsmWriter", ":PPCGenAsmWriter",
":PPCGenMCCodeEmitter", ":PPCGenMCCodeEmitter",
"//llvm/lib/MC", "//llvm/lib/MC",
"//llvm/lib/Support", "//llvm/lib/Support",
"//llvm/lib/Target/PowerPC/TargetInfo", "//llvm/lib/Target/PowerPC/TargetInfo",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
Show All 12 Lines

llvm/trunk/utils/gn/secondary/llvm/lib/Target/PowerPC/TargetInfo/BUILD.gn

static_library("TargetInfo") { static_library("TargetInfo") {
output_name = "LLVMPowerPCInfo" output_name = "LLVMPowerPCInfo"
deps = [ deps = [
"//llvm/lib/Support", "//llvm/lib/Support",
# MCTargetDesc depends on TargetInfo, so we can't depend on the full
# MCTargetDesc target here: it would form a cycle.
"//llvm/lib/Target/PowerPC/MCTargetDesc:tablegen",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
sources = [ sources = [
"PowerPCTargetInfo.cpp", "PowerPCTargetInfo.cpp",
] ]
} }

llvm/trunk/utils/gn/secondary/llvm/lib/Target/RISCV/Utils/BUILD.gn

import("//llvm/utils/TableGen/tablegen.gni") import("//llvm/utils/TableGen/tablegen.gni")
tablegen("RISCVGenSystemOperands") { tablegen("RISCVGenSystemOperands") {
visibility = [ ":Utils" ] visibility = [ ":Utils" ]
args = [ "-gen-searchable-tables" ] args = [ "-gen-searchable-tables" ]
td_file = "../RISCV.td" td_file = "../RISCV.td"
} }
static_library("Utils") { static_library("Utils") {
output_name = "LLVMRISCVUtils" output_name = "LLVMRISCVUtils"
public_deps = [ public_deps = [
":RISCVGenSystemOperands", ":RISCVGenSystemOperands",
] ]
deps = [ deps = [
"//llvm/lib/MC", "//llvm/lib/MC",
"//llvm/lib/Support", "//llvm/lib/Support",
# MCTargetDesc depends on Utils, so we can't depend on the full
# MCTargetDesc target here: it would form a cycle.
"//llvm/lib/Target/RISCV/MCTargetDesc:tablegen", "//llvm/lib/Target/RISCV/MCTargetDesc:tablegen",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
sources = [ sources = [
"RISCVBaseInfo.cpp", "RISCVBaseInfo.cpp",
"RISCVMatInt.cpp", "RISCVMatInt.cpp",
] ]
} }

llvm/trunk/utils/gn/secondary/llvm/lib/Target/Sparc/MCTargetDesc/BUILD.gn

import("//llvm/utils/TableGen/tablegen.gni") import("//llvm/utils/TableGen/tablegen.gni")
tablegen("SparcGenAsmWriter") { tablegen("SparcGenAsmWriter") {
visibility = [ ":MCTargetDesc" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-asm-writer" ] args = [ "-gen-asm-writer" ]
td_file = "../Sparc.td" td_file = "../Sparc.td"
} }
tablegen("SparcGenInstrInfo") { tablegen("SparcGenInstrInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-instr-info" ] args = [ "-gen-instr-info" ]
td_file = "../Sparc.td" td_file = "../Sparc.td"
} }
tablegen("SparcGenMCCodeEmitter") { tablegen("SparcGenMCCodeEmitter") {
visibility = [ ":MCTargetDesc" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-emitter" ] args = [ "-gen-emitter" ]
td_file = "../Sparc.td" td_file = "../Sparc.td"
} }
tablegen("SparcGenRegisterInfo") { tablegen("SparcGenRegisterInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-register-info" ] args = [ "-gen-register-info" ]
td_file = "../Sparc.td" td_file = "../Sparc.td"
} }
tablegen("SparcGenSubtargetInfo") { tablegen("SparcGenSubtargetInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-subtarget" ] args = [ "-gen-subtarget" ]
td_file = "../Sparc.td" td_file = "../Sparc.td"
} }
static_library("MCTargetDesc") {
output_name = "LLVMSparcDesc"
# This should contain tablegen targets generating .inc files included # This should contain tablegen targets generating .inc files included
# by other targets. .inc files only used by .cpp files in this directory # by other targets. .inc files only used by .cpp files in this directory
# should be in deps on the static_library instead. # should be in deps instead.
group("tablegen") {
visibility = [
":MCTargetDesc",
"../TargetInfo",
]
public_deps = [ public_deps = [
":SparcGenInstrInfo", ":SparcGenInstrInfo",
":SparcGenRegisterInfo", ":SparcGenRegisterInfo",
":SparcGenSubtargetInfo", ":SparcGenSubtargetInfo",
] ]
}
static_library("MCTargetDesc") {
output_name = "LLVMSparcDesc"
public_deps = [
":tablegen",
]
deps = [ deps = [
":SparcGenAsmWriter", ":SparcGenAsmWriter",
":SparcGenMCCodeEmitter", ":SparcGenMCCodeEmitter",
"//llvm/lib/MC", "//llvm/lib/MC",
"//llvm/lib/Support", "//llvm/lib/Support",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
sources = [ sources = [
Show All 10 Lines

llvm/trunk/utils/gn/secondary/llvm/lib/Target/Sparc/TargetInfo/BUILD.gn

static_library("TargetInfo") { static_library("TargetInfo") {
output_name = "LLVMSparcInfo" output_name = "LLVMSparcInfo"
deps = [ deps = [
"//llvm/lib/IR",
"//llvm/lib/Support", "//llvm/lib/Support",
"//llvm/lib/Target/Sparc/MCTargetDesc",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
sources = [ sources = [
"SparcTargetInfo.cpp", "SparcTargetInfo.cpp",
] ]
} }

llvm/trunk/utils/gn/secondary/llvm/lib/Target/WebAssembly/MCTargetDesc/BUILD.gn

import("//llvm/utils/TableGen/tablegen.gni") import("//llvm/utils/TableGen/tablegen.gni")
tablegen("WebAssemblyGenAsmWriter") { tablegen("WebAssemblyGenAsmWriter") {
visibility = [ ":MCTargetDesc" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-asm-writer" ] args = [ "-gen-asm-writer" ]
td_file = "../WebAssembly.td" td_file = "../WebAssembly.td"
} }
tablegen("WebAssemblyGenInstrInfo") { tablegen("WebAssemblyGenInstrInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-instr-info" ] args = [ "-gen-instr-info" ]
td_file = "../WebAssembly.td" td_file = "../WebAssembly.td"
} }
tablegen("WebAssemblyGenMCCodeEmitter") { tablegen("WebAssemblyGenMCCodeEmitter") {
visibility = [ ":MCTargetDesc" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-emitter" ] args = [ "-gen-emitter" ]
td_file = "../WebAssembly.td" td_file = "../WebAssembly.td"
} }
tablegen("WebAssemblyGenRegisterInfo") { tablegen("WebAssemblyGenRegisterInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-register-info" ] args = [ "-gen-register-info" ]
td_file = "../WebAssembly.td" td_file = "../WebAssembly.td"
} }
tablegen("WebAssemblyGenSubtargetInfo") { tablegen("WebAssemblyGenSubtargetInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-subtarget" ] args = [ "-gen-subtarget" ]
td_file = "../WebAssembly.td" td_file = "../WebAssembly.td"
} }
static_library("MCTargetDesc") {
output_name = "LLVMWebAssemblyDesc"
# This should contain tablegen targets generating .inc files included # This should contain tablegen targets generating .inc files included
# by other targets. .inc files only used by .cpp files in this directory # by other targets. .inc files only used by .cpp files in this directory
# should be in deps on the static_library instead. # should be in deps instead.
group("tablegen") {
visibility = [
":MCTargetDesc",
"../InstPrinter",
"../TargetInfo",
"../Utils",
]
public_deps = [ public_deps = [
":WebAssemblyGenInstrInfo", ":WebAssemblyGenInstrInfo",
":WebAssemblyGenRegisterInfo", ":WebAssemblyGenRegisterInfo",
":WebAssemblyGenSubtargetInfo", ":WebAssemblyGenSubtargetInfo",
] ]
}
static_library("MCTargetDesc") {
output_name = "LLVMWebAssemblyDesc"
public_deps = [
":tablegen",
]
deps = [ deps = [
":WebAssemblyGenAsmWriter", ":WebAssemblyGenAsmWriter",
":WebAssemblyGenMCCodeEmitter", ":WebAssemblyGenMCCodeEmitter",
"//llvm/lib/MC", "//llvm/lib/MC",
"//llvm/lib/Support", "//llvm/lib/Support",
"//llvm/lib/Target/WebAssembly/TargetInfo", "//llvm/lib/Target/WebAssembly/TargetInfo",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
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llvm/trunk/utils/gn/secondary/llvm/lib/Target/WebAssembly/TargetInfo/BUILD.gn

static_library("TargetInfo") { static_library("TargetInfo") {
output_name = "LLVMWebAssemblyInfo" output_name = "LLVMWebAssemblyInfo"
deps = [ deps = [
"//llvm/lib/Support", "//llvm/lib/Support",
# MCTargetDesc depends on TargetInfo, so we can't depend on the full
# MCTargetDesc target here: it would form a cycle.
"//llvm/lib/Target/WebAssembly/MCTargetDesc:tablegen",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
sources = [ sources = [
"WebAssemblyTargetInfo.cpp", "WebAssemblyTargetInfo.cpp",
] ]
} }

llvm/trunk/utils/gn/secondary/llvm/lib/Target/X86/MCTargetDesc/BUILD.gn

Show All 10 Linestablegen("X86GenAsmWriter1") {
args = [ args = [
"-gen-asm-writer", "-gen-asm-writer",
"-asmwriternum=1", "-asmwriternum=1",
] ]
td_file = "../X86.td" td_file = "../X86.td"
} }
tablegen("X86GenInstrInfo") { tablegen("X86GenInstrInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-instr-info" ] args = [ "-gen-instr-info" ]
td_file = "../X86.td" td_file = "../X86.td"
} }
tablegen("X86GenRegisterInfo") { tablegen("X86GenRegisterInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-register-info" ] args = [ "-gen-register-info" ]
td_file = "../X86.td" td_file = "../X86.td"
} }
tablegen("X86GenSubtargetInfo") { tablegen("X86GenSubtargetInfo") {
visibility = [ ":tablegen" ] visibility = [ ":MCTargetDesc" ]
args = [ "-gen-subtarget" ] args = [ "-gen-subtarget" ]
td_file = "../X86.td" td_file = "../X86.td"
} }
static_library("MCTargetDesc") {
output_name = "LLVMX86Desc"
# This should contain tablegen targets generating .inc files included # This should contain tablegen targets generating .inc files included
# by other targets. .inc files only used by .cpp files in this directory # by other targets. .inc files only used by .cpp files in this directory
# should be in deps on the static_library instead. # should be in deps instead.
group("tablegen") {
visibility = [
":MCTargetDesc",
"../TargetInfo",
]
public_deps = [ public_deps = [
":X86GenInstrInfo", ":X86GenInstrInfo",
":X86GenRegisterInfo", ":X86GenRegisterInfo",
":X86GenSubtargetInfo", ":X86GenSubtargetInfo",
] ]
}
static_library("MCTargetDesc") {
output_name = "LLVMX86Desc"
public_deps = [
":tablegen",
]
deps = [ deps = [
":X86GenAsmWriter", ":X86GenAsmWriter",
":X86GenAsmWriter1", ":X86GenAsmWriter1",
"//llvm/lib/MC", "//llvm/lib/MC",
"//llvm/lib/MC/MCDisassembler", "//llvm/lib/MC/MCDisassembler",
"//llvm/lib/Object", "//llvm/lib/Object",
"//llvm/lib/Support", "//llvm/lib/Support",
"//llvm/lib/Target/X86/TargetInfo", "//llvm/lib/Target/X86/TargetInfo",
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llvm/trunk/utils/gn/secondary/llvm/lib/Target/X86/TargetInfo/BUILD.gn

static_library("TargetInfo") { static_library("TargetInfo") {
output_name = "LLVMX86Info" output_name = "LLVMX86Info"
deps = [ deps = [
"//llvm/lib/Support", "//llvm/lib/Support",
# MCTargetDesc depends on TargetInfo, so we can't depend on the full
# MCTargetDesc target here: it would form a cycle.
"//llvm/lib/Target/X86/MCTargetDesc:tablegen",
] ]
include_dirs = [ ".." ] include_dirs = [ ".." ]
sources = [ sources = [
"X86TargetInfo.cpp", "X86TargetInfo.cpp",
] ]
} }