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Differential D63027

AMDGPU: Force skips around traps
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Authored by arsenm on Jun 7 2019, 2:27 PM.

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rampitec

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Event Timeline

arsenm created this revision.Jun 7 2019, 2:27 PM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptJun 7 2019, 2:27 PM
rampitec accepted this revision.Jun 7 2019, 3:53 PM

LGTM

This revision is now accepted and ready to land.Jun 7 2019, 3:53 PM
arsenm closed this revision.Jun 7 2019, 3:59 PM

r362852

Revision Contents

PathSize
lib/
Target/
AMDGPU/
2 lines
test/
CodeGen/
AMDGPU/
58 lines

Diff 203625

lib/Target/AMDGPU/SIInstrInfo.cpp

Show First 20 Lines • Show All 2,492 Lines • ▼ Show 20 Linesbool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const {
// These instructions cause shader I/O that may cause hardware lockups // These instructions cause shader I/O that may cause hardware lockups
// when executed with an empty EXEC mask. // when executed with an empty EXEC mask.
// //
// Note: exp with VM = DONE = 0 is automatically skipped by hardware when // Note: exp with VM = DONE = 0 is automatically skipped by hardware when
// EXEC = 0, but checking for that case here seems not worth it // EXEC = 0, but checking for that case here seems not worth it
// given the typical code patterns. // given the typical code patterns.
if (Opcode == AMDGPU::S_SENDMSG || Opcode == AMDGPU::S_SENDMSGHALT || if (Opcode == AMDGPU::S_SENDMSG || Opcode == AMDGPU::S_SENDMSGHALT ||
Opcode == AMDGPU::EXP || Opcode == AMDGPU::EXP_DONE || Opcode == AMDGPU::EXP || Opcode == AMDGPU::EXP_DONE ||
Opcode == AMDGPU::DS_ORDERED_COUNT) Opcode == AMDGPU::DS_ORDERED_COUNT || Opcode == AMDGPU::S_TRAP)
return true; return true;
if (MI.isCall() || MI.isInlineAsm()) if (MI.isCall() || MI.isInlineAsm())
return true; // conservative assumption return true; // conservative assumption
// These are like SALU instructions in terms of effects, so it's questionable // These are like SALU instructions in terms of effects, so it's questionable
// whether we should return true for those. // whether we should return true for those.
// //
▲ Show 20 Lines • Show All 3,458 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/skip-branch-trap.ll

  • This file was added.
; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=HSA-TRAP %s
; FIXME: merge with trap.ll
; An s_cbranch_execnz is required to avoid trapping if all lanes are 0
; GCN-LABEL: {{^}}trap_divergent_branch:
; GCN: s_and_saveexec_b64
; GCN: s_cbranch_execz [[ENDPGM:BB[0-9]+_[0-9]+]]
; GCN: s_branch [[TRAP:BB[0-9]+_[0-9]+]]
; GCN: [[ENDPGM]]:
; GCN-NEXT: s_endpgm
; GCN: [[TRAP]]:
; GCN: s_trap 2
; GCN-NEXT: s_endpgm
define amdgpu_kernel void @trap_divergent_branch(i32 addrspace(1)* nocapture readonly %arg) {
%id = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
%divergent.val = load i32, i32 addrspace(1)* %gep
%cmp = icmp eq i32 %divergent.val, 0
br i1 %cmp, label %bb, label %end
bb:
call void @llvm.trap()
br label %end
end:
ret void
}
; GCN-LABEL: {{^}}debugtrap_divergent_branch:
; GCN: s_and_saveexec_b64
; GCN: s_cbranch_execz [[ENDPGM:BB[0-9]+_[0-9]+]]
; GCN: BB{{[0-9]+}}_{{[0-9]+}}:
; GCN: s_trap 3
; GCN-NEXT: [[ENDPGM]]:
; GCN-NEXT: s_endpgm
define amdgpu_kernel void @debugtrap_divergent_branch(i32 addrspace(1)* nocapture readonly %arg) {
%id = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
%divergent.val = load i32, i32 addrspace(1)* %gep
%cmp = icmp eq i32 %divergent.val, 0
br i1 %cmp, label %bb, label %end
bb:
call void @llvm.debugtrap()
br label %end
end:
ret void
}
declare void @llvm.trap() #0
declare void @llvm.debugtrap() #1
declare i32 @llvm.amdgcn.workitem.id.x() #2
attributes #0 = { nounwind noreturn }
attributes #1 = { nounwind }
attributes #2 = { nounwind readnone speculatable }