[mips] Extend range of register indexes accepted by cfcmsa/ctcmsa

[atanasyan]

Summary

The cfcmsa and ctcmsa instructions accept index of MSA control register. The MIPS64 SIMD Architecture define eight MSA control registers. But register index for cfcmsa and ctcmsa instructions might be any number in 0..31 range. If the index is greater then 7, cfcmsa writes zero to the destination registers and ctcmsa does nothing [1].

[1] MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module
https://www.mips.com/?do-download=the-mips64-simd-architecture-module

[Petar.Avramovic]

LGTM.

llvm/lib/Target/Mips/MipsRegisterInfo.td

let Namespace = "Mips" in {
   def MSAIR      : MipsReg<0, "0">;
   def MSACSR     : MipsReg<1, "1">;
   def MSAAccess  : MipsReg<2, "2">;
   def MSASave    : MipsReg<3, "3">;
   def MSAModify  : MipsReg<4, "4">;
   def MSARequest : MipsReg<5, "5">;
   def MSAMap     : MipsReg<6, "6">;
   def MSAUnmap   : MipsReg<7, "7">;
+  // MSA-ASE fake control registers.
+  // These registers do not exist, but instructions like `cfcmsa`
+  // and `ctcmsa` allows to specify them.
+  foreach I = 8-31 in
+  def MSA#I : MipsReg<#I, ""#I>;
 
   // Octeon multiplier and product registers
   def MPL0 : MipsReg<0, "mpl0">;
   def MPL1 : MipsReg<1, "mpl1">;
   def MPL2 : MipsReg<2, "mpl2">;
   def P0 : MipsReg<0, "p0">;
   def P1 : MipsReg<1, "p1">;
   def P2 : MipsReg<2, "p2">;

 def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128,
                            (sequence "W%u", 0, 31)>;
 def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128,
                            (sequence "W%u", 0, 31)>;
 def MSA128WEvens: RegisterClass<"Mips", [v4i32, v4f32], 128,
                                 (decimate (sequence "W%u", 0, 31), 2)>;
 
 def MSACtrl: RegisterClass<"Mips", [i32], 32, (add
-  MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>;
+  MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap,
+  (sequence "MSA%u", 8, 31))>, Unallocatable;
 
 // Hi/Lo Registers
 def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;
 def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>;
 def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>;
 def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>;
 def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>;
 def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>;

llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp

void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
   if (Mask & 16)
     MIB.addReg(Mips::DSPCCond, Flag);
 
   if (Mask & 32)
     MIB.addReg(Mips::DSPEFI, Flag);
 }
 
 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
-  switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
-  default:
-    llvm_unreachable("Could not map int to register");
-  case 0: return Mips::MSAIR;
-  case 1: return Mips::MSACSR;
-  case 2: return Mips::MSAAccess;
-  case 3: return Mips::MSASave;
-  case 4: return Mips::MSAModify;
-  case 5: return Mips::MSARequest;
-  case 6: return Mips::MSAMap;
-  case 7: return Mips::MSAUnmap;
-  }
+  uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue();
+  return Mips::MSACtrlRegClass.getRegister(RegNum);
 }
 
 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
                                                 const MachineInstr& MI) {
   unsigned DstReg = 0, ZeroReg = 0;
 
   // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
   if ((MI.getOpcode() == Mips::ADDiu) &&

llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll

entry:
   %0 = tail call i32 @llvm.mips.cfcmsa(i32 7)
   ret i32 %0
 }
 
 ; CHECK: msa_unmap_cfcmsa_test:
 ; CHECK: cfcmsa $[[R1:[0-9]+]], $7
 ; CHECK: .size msa_unmap_cfcmsa_test
 ;
+define i32 @msa_invalid_reg_cfcmsa_test() nounwind {
+entry:
+  %0 = tail call i32 @llvm.mips.cfcmsa(i32 8)
+  ret i32 %0
+}
+
+; CHECK-LABEL: msa_invalid_reg_cfcmsa_test:
+; CHECK: cfcmsa ${{[0-9]+}}, $8
+;
 define void @msa_ir_ctcmsa_test() nounwind {
 entry:
   tail call void @llvm.mips.ctcmsa(i32 0, i32 1)
   ret void
 }
 
 ; CHECK: msa_ir_ctcmsa_test:
 ; CHECK: ctcmsa $0
entry:
   tail call void @llvm.mips.ctcmsa(i32 7, i32 1)
   ret void
 }
 
 ; CHECK: msa_unmap_ctcmsa_test:
 ; CHECK: ctcmsa $7
 ; CHECK: .size msa_unmap_ctcmsa_test
 ;
+define void @msa_invalid_reg_ctcmsa_test() nounwind {
+entry:
+  tail call void @llvm.mips.ctcmsa(i32 8, i32 1)
+  ret void
+}
+
+; CHECK: msa_invalid_reg_ctcmsa_test:
+; CHECK: ctcmsa $8
+;
 declare i32 @llvm.mips.cfcmsa(i32) nounwind
 declare void @llvm.mips.ctcmsa(i32, i32) nounwind