This copies the Sandy Bridge zero idiom support to later CPUs. Adding the AVX2 and AVX512F/VL instructions as appropriate.
Details
Diff Detail
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- rL LLVM
Event Timeline
llvm/lib/Target/X86/X86SchedSandyBridge.td | ||
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1163 ↗ | (On Diff #201105) | I didn't like the reference to ResGroup30 since someone could easily rearrange numbers and not know this was dependent. So I copied the class and gave it a better name. |
Thanks.
llvm/lib/Target/X86/X86SchedSandyBridge.td | ||
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1163 ↗ | (On Diff #201105) | Makes sense. |
pre-commit the zero idiom tests?
llvm/lib/Target/X86/X86SchedBroadwell.td | ||
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1606 ↗ | (On Diff #201105) | Haswell and Broadwell? |
llvm/lib/Target/X86/X86SchedHaswell.td | ||
1859 ↗ | (On Diff #201105) | Haswell and Broadwell? |
llvm/lib/Target/X86/X86SchedSkylakeClient.td | ||
1747 ↗ | (On Diff #201105) | Skylake? |
llvm/lib/Target/X86/X86SchedSkylakeServer.td | ||
2463 ↗ | (On Diff #201105) | Skylake? |
LGTM (modulo the changes requested by Simon).
Thanks Craig!
About PR41982:
It would be really nice if we could teach llvm-mca how to identify dependency-breaking idioms.
That could be done in a follow-up patch by adding some extra tablegen definitions to those scheduling models.
For example, on BtVer2 we have something like this:
def : IsZeroIdiomFunction<[ // GPR Zero-idioms. DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate> ... ]>;
In general, we can propagate information about dependency-breaking instructions to llvm-mca by instantiating tablegen class IsZeroIdiomFunction and IsDepBreakingFunction.
llvm-mca uses that information to accurately identify register dependencies.
Obviously, this is entirely optional; at the moment, only llvm-mca uses those definitions. Personally, I am already very happy to see this patch.
But I think that at some point we should consider adding those extra definitions in order to fully address PR41982.
Thanks,
-Andrea