Was looking into supporting (srl (shl x, c1), c2) with c1 != c2 in dagcombiner,
this test changes, but makes update_llc_test_checks.py unhappy
Details
Details
Diff Detail
Diff Detail
- Repository
- rL LLVM
Event Timeline
Comment Actions
LGTM
utils/UpdateTestChecks/asm.py | ||
---|---|---|
234 ↗ | (On Diff #200139) | pedantic - please can you put this with the other aarch64 entry at line 209? |