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Differential D6169

[mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions
ClosedPublic

Authored by jkolek on Nov 7 2014, 9:37 AM.

Details

Reviewers
sstankovic
dsanders
vmedic
Commits
rGffeed44190d8: [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.
rL222355: [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.
Summary

Fix opcodes of microMIPS MFHC1 and MTHC1 instructions, ie. instruction bits 13-6.

Diff Detail

Event Timeline

jkolek updated this revision to Diff 15929.Nov 7 2014, 9:37 AM
jkolek retitled this revision from to [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.
jkolek updated this object.
jkolek edited the test plan for this revision. (Show Details)
jkolek added reviewers: dsanders, sstankovic, vmedic.
jkolek added a subscriber: zoran.jovanovic.
sstankovic edited edge metadata.Nov 12 2014, 7:38 AM

LGTM, with two changes.

lib/Target/Mips/MicroMipsInstrFPU.td
127

You can place AdditionalRequires on the previous line. It fits in 80 columns.

130

Same here.

sstankovic accepted this revision.Nov 12 2014, 7:38 AM
sstankovic edited edge metadata.
This revision is now accepted and ready to land.Nov 12 2014, 7:38 AM
jkolek edited edge metadata.Nov 18 2014, 5:38 AM
jkolek added a subscriber: Unknown Object (MLST).
jkolek updated this revision to Diff 16335.Nov 18 2014, 7:21 AM
jkolek closed this revision.Nov 19 2014, 5:38 AM
jkolek updated this revision to Diff 16384.

Closed by commit rL222355 (authored by @jkolek).

Revision Contents

PathSize
lib/
Target/
Mips/
8 lines
test/
MC/
Mips/
6 lines

Diff 16335

lib/Target/Mips/MicroMipsInstrFPU.td

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
MFC1_FM_MM<0x40>; MFC1_FM_MM<0x40>;
def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
MFC1_FM_MM<0x60>; MFC1_FM_MM<0x60>;
def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
II_MFC1, bitconvert>, MFC1_FM_MM<0x80>; II_MFC1, bitconvert>, MFC1_FM_MM<0x80>;
def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>; II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>;
def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, II_MFHC1>, def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
MFC1_FM_MM<3>, ISA_MIPS32R2; MFC1_FM_MM<0xc0>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
sstankovicUnsubmitted
Not Done
ReplyInline Actions

You can place AdditionalRequires on the previous line. It fits in 80 columns.

sstankovic: You can place AdditionalRequires on the previous line. It fits in 80 columns.
def MTHC1_MM : MMRel, MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, II_MTHC1>, def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM_MM<7>, ISA_MIPS32R2; MFC1_FM_MM<0xe0>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
sstankovicUnsubmitted
Not Done
ReplyInline Actions

Same here.

sstankovic: Same here.
def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
MADDS_FM_MM<0x1>; MADDS_FM_MM<0x1>;
def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
MADDS_FM_MM<0x21>; MADDS_FM_MM<0x21>;
def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
MADDS_FM_MM<0x2>; MADDS_FM_MM<0x2>;
def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
MADDS_FM_MM<0x22>; MADDS_FM_MM<0x22>;
Show All 10 Lines

test/MC/Mips/micromips-fpu-instructions.s

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
# CHECK-EL: cvt.d.s $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x13] # CHECK-EL: cvt.d.s $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x13]
# CHECK-EL: cvt.d.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x33] # CHECK-EL: cvt.d.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x33]
# CHECK-EL: cvt.s.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x1b] # CHECK-EL: cvt.s.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x1b]
# CHECK-EL: cvt.s.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x3b] # CHECK-EL: cvt.s.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x3b]
# CHECK-EL: cfc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x10] # CHECK-EL: cfc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x10]
# CHECK-EL: ctc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x18] # CHECK-EL: ctc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x18]
# CHECK-EL: mfc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x20] # CHECK-EL: mfc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x20]
# CHECK-EL: mtc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x28] # CHECK-EL: mtc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x28]
# CHECK-EL: mfhc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x30]
# CHECK-EL: mthc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x38]
# CHECK-EL: movz.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x20] # CHECK-EL: movz.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x20]
# CHECK-EL: movz.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x21] # CHECK-EL: movz.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x21]
# CHECK-EL: movn.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x20] # CHECK-EL: movn.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x20]
# CHECK-EL: movn.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x21] # CHECK-EL: movn.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x21]
# CHECK-EL: movt.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x00] # CHECK-EL: movt.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x00]
# CHECK-EL: movt.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x02] # CHECK-EL: movt.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x02]
# CHECK-EL: movf.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x00] # CHECK-EL: movf.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x00]
# CHECK-EL: movf.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x02] # CHECK-EL: movf.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x02]
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
# CHECK-EB: cvt.d.s $f6, $f8 # encoding: [0x54,0xc8,0x13,0x7b] # CHECK-EB: cvt.d.s $f6, $f8 # encoding: [0x54,0xc8,0x13,0x7b]
# CHECK-EB: cvt.d.w $f6, $f8 # encoding: [0x54,0xc8,0x33,0x7b] # CHECK-EB: cvt.d.w $f6, $f8 # encoding: [0x54,0xc8,0x33,0x7b]
# CHECK-EB: cvt.s.d $f6, $f8 # encoding: [0x54,0xc8,0x1b,0x7b] # CHECK-EB: cvt.s.d $f6, $f8 # encoding: [0x54,0xc8,0x1b,0x7b]
# CHECK-EB: cvt.s.w $f6, $f8 # encoding: [0x54,0xc8,0x3b,0x7b] # CHECK-EB: cvt.s.w $f6, $f8 # encoding: [0x54,0xc8,0x3b,0x7b]
# CHECK-EB: cfc1 $6, $0 # encoding: [0x54,0xc0,0x10,0x3b] # CHECK-EB: cfc1 $6, $0 # encoding: [0x54,0xc0,0x10,0x3b]
# CHECK-EB: ctc1 $6, $0 # encoding: [0x54,0xc0,0x18,0x3b] # CHECK-EB: ctc1 $6, $0 # encoding: [0x54,0xc0,0x18,0x3b]
# CHECK-EB: mfc1 $6, $f8 # encoding: [0x54,0xc8,0x20,0x3b] # CHECK-EB: mfc1 $6, $f8 # encoding: [0x54,0xc8,0x20,0x3b]
# CHECK-EB: mtc1 $6, $f8 # encoding: [0x54,0xc8,0x28,0x3b] # CHECK-EB: mtc1 $6, $f8 # encoding: [0x54,0xc8,0x28,0x3b]
# CHECK-EB: mfhc1 $6, $f8 # encoding: [0x54,0xc8,0x30,0x3b]
# CHECK-EB: mthc1 $6, $f8 # encoding: [0x54,0xc8,0x38,0x3b]
# CHECK-EB: movz.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x78] # CHECK-EB: movz.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x78]
# CHECK-EB: movz.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x78] # CHECK-EB: movz.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x78]
# CHECK-EB: movn.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x38] # CHECK-EB: movn.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x38]
# CHECK-EB: movn.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x38] # CHECK-EB: movn.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x38]
# CHECK-EB: movt.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x60] # CHECK-EB: movt.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x60]
# CHECK-EB: movt.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x60] # CHECK-EB: movt.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x60]
# CHECK-EB: movf.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x20] # CHECK-EB: movf.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x20]
# CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20] # CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20]
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines# CHECK-EB: nmsub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x2a]
cvt.d.s $f6, $f8 cvt.d.s $f6, $f8
cvt.d.w $f6, $f8 cvt.d.w $f6, $f8
cvt.s.d $f6, $f8 cvt.s.d $f6, $f8
cvt.s.w $f6, $f8 cvt.s.w $f6, $f8
cfc1 $6, $0 cfc1 $6, $0
ctc1 $6, $0 ctc1 $6, $0
mfc1 $6, $f8 mfc1 $6, $f8
mtc1 $6, $f8 mtc1 $6, $f8
mfhc1 $6, $f8
mthc1 $6, $f8
movz.s $f4, $f6, $7 movz.s $f4, $f6, $7
movz.d $f4, $f6, $7 movz.d $f4, $f6, $7
movn.s $f4, $f6, $7 movn.s $f4, $f6, $7
movn.d $f4, $f6, $7 movn.d $f4, $f6, $7
movt.s $f4, $f6, $fcc0 movt.s $f4, $f6, $fcc0
movt.d $f4, $f6, $fcc0 movt.d $f4, $f6, $fcc0
movf.s $f4, $f6, $fcc0 movf.s $f4, $f6, $fcc0
movf.d $f4, $f6, $fcc0 movf.d $f4, $f6, $fcc0
madd.s $f2, $f4, $f6, $f8 madd.s $f2, $f4, $f6, $f8
madd.d $f2, $f4, $f6, $f8 madd.d $f2, $f4, $f6, $f8
msub.s $f2, $f4, $f6, $f8 msub.s $f2, $f4, $f6, $f8
msub.d $f2, $f4, $f6, $f8 msub.d $f2, $f4, $f6, $f8
nmadd.s $f2, $f4, $f6, $f8 nmadd.s $f2, $f4, $f6, $f8
nmadd.d $f2, $f4, $f6, $f8 nmadd.d $f2, $f4, $f6, $f8
nmsub.s $f2, $f4, $f6, $f8 nmsub.s $f2, $f4, $f6, $f8
nmsub.d $f2, $f4, $f6, $f8 nmsub.d $f2, $f4, $f6, $f8