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AMDGPU: Remove redundant patterns for shifts
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Authored by arsenm on May 2 2019, 4:14 AM.

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rampitec
arsenm

Commits

rZORG06f9e86bd91f: AMDGPU: Fix a mis-placed bracket
rZORG67d265fd6b9f: AMDGPU: Fix a mis-placed bracket
rG06f9e86bd91f: AMDGPU: Fix a mis-placed bracket
rG67d265fd6b9f: AMDGPU: Fix a mis-placed bracket
rG73b7272e7a87: AMDGPU: Fix a mis-placed bracket
rL360283: AMDGPU: Fix a mis-placed bracket

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Event Timeline

arsenm created this revision.May 2 2019, 4:14 AM

Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptMay 2 2019, 4:14 AM

rampitec added inline comments.May 2 2019, 11:52 AM

lib/Target/AMDGPU/VOP2Instructions.td
522	Did you find out why added complexity was used?

arsenm marked an inline comment as done.May 2 2019, 12:19 PM

arsenm added inline comments.

lib/Target/AMDGPU/VOP2Instructions.td
522	I assume this was to give priority to these over the _e32 ones for some reason. Nothing broke when I removed either set

Extra prechecks passed

This revision is now accepted and ready to land.May 3 2019, 8:07 AM

arsenm closed this revision.May 3 2019, 8:07 AM

rampitec added inline comments.May 7 2019, 3:42 PM

lib/Target/AMDGPU/VOP2Instructions.td
537	This is error, brace should not include adde/sube.

Revision Contents

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lib/

Target/

AMDGPU/

VOP2Instructions.td

13 lines

Diff 197742

lib/Target/AMDGPU/VOP2Instructions.td

Show First 20 Lines • Show All 513 Lines • ▼ Show 20 Lines	class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
GCNPat<		GCNPat<
(getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),		(getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
!if(!cast<Commutable_REV>(Inst).IsOrig,		!if(!cast<Commutable_REV>(Inst).IsOrig,
(Inst $src0, $src1, 0),		(Inst $src0, $src1, 0),
(Inst $src1, $src0, 0)		(Inst $src1, $src0, 0)
)		)
>;		>;

let AddedComplexity = 1 in {
rampitecUnsubmitted Not Done Reply Inline Actions Did you find out why added complexity was used? rampitec: Did you find out why added complexity was used?
arsenmAuthorUnsubmitted Done Reply Inline Actions I assume this was to give priority to these over the _e32 ones for some reason. Nothing broke when I removed either set arsenm: I assume this was to give priority to these over the _e32 ones for some reason. Nothing broke…
def : DivergentBinOp<srl, V_LSHRREV_B32_e64>;		def : DivergentBinOp<srl, V_LSHRREV_B32_e64>;
def : DivergentBinOp<sra, V_ASHRREV_I32_e64>;		def : DivergentBinOp<sra, V_ASHRREV_I32_e64>;
def : DivergentBinOp<shl, V_LSHLREV_B32_e64>;		def : DivergentBinOp<shl, V_LSHLREV_B32_e64>;
}

let SubtargetPredicate = HasAddNoCarryInsts in {		let SubtargetPredicate = HasAddNoCarryInsts in {
def : DivergentBinOp<add, V_ADD_U32_e32>;		def : DivergentBinOp<add, V_ADD_U32_e32>;
def : DivergentBinOp<sub, V_SUB_U32_e32>;		def : DivergentBinOp<sub, V_SUB_U32_e32>;
}		}

let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in {		let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in {
def : DivergentBinOp<add, V_ADD_I32_e32>;		def : DivergentBinOp<add, V_ADD_I32_e32>;
def : DivergentBinOp<sub, V_SUB_I32_e32>;		def : DivergentBinOp<sub, V_SUB_I32_e32>;

def : DivergentBinOp<srl, V_LSHRREV_B32_e32>;
def : DivergentBinOp<sra, V_ASHRREV_I32_e32>;
def : DivergentBinOp<shl, V_LSHLREV_B32_e32>;
}
def : DivergentBinOp<adde, V_ADDC_U32_e32>;		def : DivergentBinOp<adde, V_ADDC_U32_e32>;
def : DivergentBinOp<sube, V_SUBB_U32_e32>;		def : DivergentBinOp<sube, V_SUBB_U32_e32>;
		}
		rampitecUnsubmitted Not Done Reply Inline Actions This is error, brace should not include adde/sube. rampitec: This is error, brace should not include adde/sube.

class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> :		class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> :
GCNPat<		GCNPat<
(getDivergentFrag<Op>.ret i64:$src0, i64:$src1),		(getDivergentFrag<Op>.ret i64:$src0, i64:$src1),
(REG_SEQUENCE VReg_64,		(REG_SEQUENCE VReg_64,
(Inst		(Inst
(i32 (EXTRACT_SUBREG $src0, sub0)),		(i32 (EXTRACT_SUBREG $src0, sub0)),
(i32 (EXTRACT_SUBREG $src1, sub0))		(i32 (EXTRACT_SUBREG $src1, sub0))
▲ Show 20 Lines • Show All 811 Lines • Show Last 20 Lines