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[X86][SSE] isHorizontalBinOp - add support for target shuffles
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Authored by RKSimon on Apr 28 2019, 1:15 PM.

Details

Summary

Add target shuffle decoding to isHorizontalBinOp as well as ISD::VECTOR_SHUFFLE support.

This does mean we can go through bitcasts so we need to bitcast the extracted args to ensure they are the correct type

Fixes PR39936 and should help with PR39920/PR39921

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Repository
rL LLVM

Event Timeline

RKSimon created this revision.Apr 28 2019, 1:15 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 28 2019, 1:15 PM
RKSimon marked an inline comment as done.Apr 28 2019, 1:20 PM
RKSimon added inline comments.
test/CodeGen/X86/phaddsub.ll
862

Just realised this test should be in haddsub.ll - if/when accepted I'll move it across as a pre-commit

spatel added inline comments.Apr 29 2019, 7:51 AM
test/CodeGen/X86/vector-shuffle-256-v4.ll
1742–1745

It's independent of this patch, but do we consider the AVX2 sequence with vpermpd+vpermpd better than the AVX1 sequence with vperm2f128+vinsertf128?

RKSimon added inline comments.Apr 29 2019, 10:00 AM
test/CodeGen/X86/vector-shuffle-256-v4.ll
1742–1745

On Intel targets the port5 pressure is about the same - as detailed on PR39920/PR39921 @craig.topper suggested that we're better off folding to a HADD if we can remove 2 shuffles - same port5 pressure but lower instruction count. I intend to look at this in a future patch by getting isHorizontalBinOp to return the #shuffles folded.

spatel accepted this revision.Apr 29 2019, 11:12 AM

LGTM

This revision is now accepted and ready to land.Apr 29 2019, 11:12 AM
This revision was automatically updated to reflect the committed changes.