[AArch64][SVE] Asm: add aliases for unpredicated bitwise logical instructions

[c-rhodes]

Summary

This patch adds aliases for element sizes .B/.H/.S to the
AND/ORR/EOR/BIC bitwise logical instructions. The assembler now accepts
these instructions with all element sizes up to 64-bit (.D). The
preferred disassembly is .D.

[ostannard]

LGTM

lib/Target/AArch64/AArch64SVEInstrInfo.td

   defm SQSUB_ZZZ : sve_int_bin_cons_arit_0<0b110, "sqsub">;
   defm UQSUB_ZZZ : sve_int_bin_cons_arit_0<0b111, "uqsub">;
 
-  def AND_ZZZ : sve_int_bin_cons_log<0b00, "and">;
-  def ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">;
-  def EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">;
-  def BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">;
+  defm AND_ZZZ : sve_int_bin_cons_log<0b00, "and">;
+  defm ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">;
+  defm EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">;
+  defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">;
 
   defm ADD_ZPmZ   : sve_int_bin_pred_arit_0<0b000, "add">;
   defm SUB_ZPmZ   : sve_int_bin_pred_arit_0<0b001, "sub">;

lib/Target/AArch64/SVEInstrFormats.td

   let Inst{4-0}   = Zd;
 }
 
+multiclass sve_int_bin_cons_log<bits<2> opc, string asm> {
+  def NAME : sve_int_bin_cons_log<opc, asm>;
+
+  def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
+                  (!cast<Instruction>(NAME) ZPR8:$Zd,  ZPR8:$Zn,  ZPR8:$Zm),  1>;
+  def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
+                  (!cast<Instruction>(NAME) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 1>;
+  def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
+                  (!cast<Instruction>(NAME) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 1>;
+}
 
 //===----------------------------------------------------------------------===//
 // SVE Integer Wide Immediate - Predicated Group

test/MC/AArch64/SVE/and.s

 
 
 // --------------------------------------------------------------------------//
+// Test aliases.
+
+and     z0.s, z0.s, z0.s
+// CHECK-INST: and     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 20 04 <unknown>
+
+and     z0.h, z0.h, z0.h
+// CHECK-INST: and     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 20 04 <unknown>
+
+and     z0.b, z0.b, z0.b
+// CHECK-INST: and     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 20 04 <unknown>
+
+
+// --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
 
 movprfx z4.d, p7/z, z6.d

test/MC/AArch64/SVE/bic.s

 
 
 // --------------------------------------------------------------------------//
+// Test aliases.
+
+bic     z0.s, z0.s, z0.s
+// CHECK-INST: bic     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
+
+bic     z0.h, z0.h, z0.h
+// CHECK-INST: bic     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
+
+bic     z0.b, z0.b, z0.b
+// CHECK-INST: bic     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
+
+
+// --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
 
 movprfx z4.d, p7/z, z6.d

test/MC/AArch64/SVE/eor.s

 
 
 // --------------------------------------------------------------------------//
+// Test aliases.
+
+eor     z0.s, z0.s, z0.s
+// CHECK-INST: eor     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
+
+eor     z0.h, z0.h, z0.h
+// CHECK-INST: eor     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
+
+eor     z0.b, z0.b, z0.b
+// CHECK-INST: eor     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
+
+
+// --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
 
 movprfx z4.b, p7/z, z6.b

test/MC/AArch64/SVE/orr.s

 
 
 // --------------------------------------------------------------------------//
+// Test aliases.
+
+orr     z0.s, z0.s, z0.s
+// CHECK-INST: mov     z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+
+orr     z0.h, z0.h, z0.h
+// CHECK-INST: mov     z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+
+orr     z0.b, z0.b, z0.b
+// CHECK-INST: mov     z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+
+orr     z23.s, z13.s, z8.s  // should not use mov-alias
+// CHECK-INST: orr     z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 31 68 04 <unknown>
+
+orr     z23.h, z13.h, z8.h  // should not use mov-alias
+// CHECK-INST: orr     z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 31 68 04 <unknown>
+
+orr     z23.b, z13.b, z8.b  // should not use mov-alias
+// CHECK-INST: orr     z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 31 68 04 <unknown>
+
+
+// --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
 
 movprfx z4.d, p7/z, z6.d