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Differential D60877

[GlobalISel][AArch64] Legalize v8s8 loads
ClosedPublic

Authored by paquette on Apr 18 2019, 9:49 AM.

Details

Reviewers
aemerson
Commits
rG3b5119c68455: [GlobalISel][AArch64] Legalize v8s8 loads
rL358714: [GlobalISel][AArch64] Legalize v8s8 loads
Summary

Add legalizer support for loads of v8s8 and update legalize-load-store.mir.

Diff Detail

Repository
rL LLVM

Event Timeline

paquette created this revision.Apr 18 2019, 9:49 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 18 2019, 9:49 AM
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls and 2 others. · View Herald Transcript
aemerson accepted this revision.Apr 18 2019, 11:21 AM
This revision is now accepted and ready to land.Apr 18 2019, 11:21 AM
Closed by commit rL358714: [GlobalISel][AArch64] Legalize v8s8 loads (authored by paquette). · Explain WhyApr 18 2019, 2:14 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AArch64/
1 line
test/
CodeGen/
AArch64/
GlobalISel/
25 lines

Diff 195814

llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp

Show First 20 Lines • Show All 218 Lines • ▼ Show 20 LinesAArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
}; };
getActionDefinitionsBuilder(G_LOAD) getActionDefinitionsBuilder(G_LOAD)
.legalForTypesWithMemDesc({{s8, p0, 8, 8}, .legalForTypesWithMemDesc({{s8, p0, 8, 8},
{s16, p0, 16, 8}, {s16, p0, 16, 8},
{s32, p0, 32, 8}, {s32, p0, 32, 8},
{s64, p0, 64, 8}, {s64, p0, 64, 8},
{p0, p0, 64, 8}, {p0, p0, 64, 8},
{v8s8, p0, 64, 8},
{v16s8, p0, 128, 8}, {v16s8, p0, 128, 8},
{v4s16, p0, 64, 8}, {v4s16, p0, 64, 8},
{v8s16, p0, 128, 8}, {v8s16, p0, 128, 8},
{v2s32, p0, 64, 8}, {v2s32, p0, 64, 8},
{v4s32, p0, 128, 8}, {v4s32, p0, 128, 8},
{v2s64, p0, 128, 8}}) {v2s64, p0, 128, 8}})
// These extends are also legal // These extends are also legal
.legalForTypesWithMemDesc({{s32, p0, 8, 8}, .legalForTypesWithMemDesc({{s32, p0, 8, 8},
▲ Show 20 Lines • Show All 426 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines define <8 x i16> @load_8xi16(<8 x i16>* %ptr) {
ret <8 x i16> %res ret <8 x i16> %res
} }
define <16 x i8> @load_16xi8(<16 x i8>* %ptr) { define <16 x i8> @load_16xi8(<16 x i8>* %ptr) {
%res = load <16 x i8>, <16 x i8>* %ptr %res = load <16 x i8>, <16 x i8>* %ptr
ret <16 x i8> %res ret <16 x i8> %res
} }
define <8 x i8> @load_8xi8(<8 x i8>* %ptr) {
%res = load <8 x i8>, <8 x i8>* %ptr
ret <8 x i8> %res
}
... ...
--- ---
name: test_load name: test_load
body: | body: |
bb.0: bb.0:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_load ; CHECK-LABEL: name: test_load
▲ Show 20 Lines • Show All 255 Lines • ▼ Show 20 Lines bb.1 (%ir-block.0):
; CHECK: $q0 = COPY [[LOAD]](<16 x s8>) ; CHECK: $q0 = COPY [[LOAD]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0 ; CHECK: RET_ReallyLR implicit $q0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr) %1:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr)
$q0 = COPY %1(<16 x s8>) $q0 = COPY %1(<16 x s8>)
RET_ReallyLR implicit $q0 RET_ReallyLR implicit $q0
... ...
---
name: load_8xi8
alignment: 2
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.1 (%ir-block.0):
liveins: $x0
; CHECK-LABEL: name: load_8xi8
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.ptr)
; CHECK: $d0 = COPY [[LOAD]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(p0) = COPY $x0
%1:_(<8 x s8>) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)
$d0 = COPY %1(<8 x s8>)
RET_ReallyLR implicit $d0
...