[MachineScheduler] Check pending instructions when an instruction is scheduled

[jmolloy]

Summary

Pending instructions that may have been blocked from being available by the HazardRecognizer may no longer may not be blocked any more when an instruction is scheduled; pending instructions should be re-checked in this case.

No testcase as no in-tree targets have this behavior and the CheckPending behavior (AFAICT) is intended only for compile performance, not correctness.

[hfinkel]

Pending instructions that may have been blocked from being available by the HazardRecognizer may no longer may not be blocked any more when an instruction is scheduled; pending instructions should be re-checked in this case.

You mean in the same cycle? Are you using the hazard recognizer to enforce some kind of co-scheduling requirement? I ask because we already set CheckPending to true in bumpCycle.

[jmolloy]

Hi Hal,

Yes, that's right. The architecture in question is VLIW, so there is plenty of available parallelism per cycle and esoteric constraints.

Cheers,

James

[hfinkel]

In D60861#1472146, @jmolloy wrote:

Hi Hal,

Yes, that's right. The architecture in question is VLIW, so there is plenty of available parallelism per cycle and esoteric constraints.

Okay, can you please update the comment to make it clear that this is specifically to support this kind of situation?

Otherwise, I think this is fine.

Cheers,

James

[jmolloy]

Thanks Hal! r358743.

llvm/trunk/lib/CodeGen/MachineScheduler.cpp

void SchedBoundary::bumpNode(SUnit *SU) {
   // Update the reservation table.
   if (HazardRec->isEnabled()) {
     if (!isTop() && SU->isCall) {
       // Calls are scheduled with their preceding instructions. For bottom-up
       // scheduling, clear the pipeline state before emitting.
       HazardRec->Reset();
     }
     HazardRec->EmitInstruction(SU);
+    // Scheduling an instruction may have made pending instructions available.
+    CheckPending = true;
   }
   // checkHazard should prevent scheduling multiple instructions per cycle that
   // exceed the issue width.
   const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
   unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr());
   assert(
       (CurrMOps == 0 || (CurrMOps + IncMOps) <= SchedModel->getIssueWidth()) &&
       "Cannot schedule this instruction's MicroOps in the current cycle.");