Revert LIS handling in MachineDCE

[rampitec]

Summary

One of out of tree targets has regressed with this patch. Reverting
it for now and let liveness to be fully reconstructed in case pass
was used after the LIS is created to resolve the regression.

[rampitec]

FYI, changes in AMDGPU tests are just because of the liveness rebuild which results in a slightly different and non important allocation change.

[bjope]

Thanks, LGTM!

nit: Maybe you want to add the reproducer for the "multiple connected intervals" for future reference?

[rampitec]

Added regression test.

llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp

 //===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This is an extremely simple MachineInstr-level dead-code-elimination pass.
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/Statistic.h"
-#include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "dead-mi-elimination"
 
 STATISTIC(NumDeletes,          "Number of dead instructions deleted");
 
 namespace {
   class DeadMachineInstructionElim : public MachineFunctionPass {
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     const TargetRegisterInfo *TRI;
     const MachineRegisterInfo *MRI;
     const TargetInstrInfo *TII;
-    LiveIntervals *LIS;
     BitVector LivePhysRegs;
 
   public:
     static char ID; // Pass identification, replacement for typeid
     DeadMachineInstructionElim() : MachineFunctionPass(ID) {
      initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry());
     }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
-      AU.setPreservesAll();
+      AU.setPreservesCFG();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
   private:
     bool isDead(const MachineInstr *MI) const;
   };
 }
 char DeadMachineInstructionElim::ID = 0;
bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
 
   // Examine each operand.
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
     if (MO.isReg() && MO.isDef()) {
       unsigned Reg = MO.getReg();
       if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
         // Don't delete live physreg defs, or any reserved register defs.
-        // Do not remove physreg defs if we have LIS as we may be unable
-        // to accurately recompute its liveness.
-        if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg) || LIS)
+        if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
           return false;
       } else {
-        // An instruction can also use its def in case if it is a tied operand.
-        // TODO: Technically we can also remove it if def dominates the use.
-        //       This can happen when two instructions define different subregs
-        //       of the same register.
         for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
           if (&Use != MI)
             // This def has a non-debug use. Don't delete the instruction!
             return false;
         }
       }
     }
   }
 
   // If there are no defs with uses, the instruction is dead.
   return true;
 }
 
 bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
   if (skipFunction(MF.getFunction()))
     return false;
 
   bool AnyChanges = false;
   MRI = &MF.getRegInfo();
   TRI = MF.getSubtarget().getRegisterInfo();
   TII = MF.getSubtarget().getInstrInfo();
-  LIS = getAnalysisIfAvailable<LiveIntervals>();
-  DenseSet<unsigned> RecalcRegs;
 
   // Loop over all instructions in all blocks, from bottom to top, so that it's
   // more likely that chains of dependent but ultimately dead instructions will
   // be cleaned up.
   for (MachineBasicBlock &MBB : make_range(MF.rbegin(), MF.rend())) {
     // Start out assuming that reserved registers are live out of this block.
     LivePhysRegs = MRI->getReservedRegs();
 
for (MachineBasicBlock &MBB : make_range(MF.rbegin(), MF.rend())) {
     // liveness as we go.
     for (MachineBasicBlock::reverse_iterator MII = MBB.rbegin(),
          MIE = MBB.rend(); MII != MIE; ) {
       MachineInstr *MI = &*MII++;
 
       // If the instruction is dead, delete it!
       if (isDead(MI)) {
         LLVM_DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
-        if (LIS) {
-          for (const MachineOperand &MO : MI->operands()) {
-            if (MO.isReg() && TRI->isVirtualRegister(MO.getReg()))
-              RecalcRegs.insert(MO.getReg());
-          }
-          LIS->RemoveMachineInstrFromMaps(*MI);
-        }
-
         // It is possible that some DBG_VALUE instructions refer to this
         // instruction.  They get marked as undef and will be deleted
         // in the live debug variable analysis.
         MI->eraseFromParentAndMarkDBGValuesForRemoval();
         AnyChanges = true;
         ++NumDeletes;
         continue;
       }
for (MachineBasicBlock::reverse_iterator MII = MBB.rbegin(),
               LivePhysRegs.set(*AI);
           }
         }
       }
     }
   }
 
   LivePhysRegs.clear();
-
-  for (auto Reg : RecalcRegs) {
-    LIS->removeInterval(Reg);
-    if (!MRI->reg_empty(Reg))
-      LIS->createAndComputeVirtRegInterval(Reg);
-  }
-
   return AnyChanges;
 }

llvm/trunk/test/CodeGen/AMDGPU/bswap.ll

; VI-NEXT:    s_endpgm
   %bswap = call i64 @llvm.bswap.i64(i64 %val) nounwind readnone
   store i64 %bswap, i64 addrspace(1)* %out, align 8
   ret void
 }
 
 define amdgpu_kernel void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) nounwind {
 ; SI-LABEL: test_bswap_v2i64:
 ; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_mov_b32 s31, 0xff0000
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_load_dwordx4 s[8:11], s[6:7], 0x0
-; SI-NEXT:    s_mov_b32 s7, 0
+; SI-NEXT:    s_load_dwordx4 s[4:7], s[10:11], 0x0
+; SI-NEXT:    s_mov_b32 s11, 0
 ; SI-NEXT:    s_mov_b32 s22, 0xff000000
 ; SI-NEXT:    s_mov_b32 s27, 0xff00
 ; SI-NEXT:    s_movk_i32 s25, 0xff
-; SI-NEXT:    s_mov_b32 s13, s7
-; SI-NEXT:    s_mov_b32 s14, s7
-; SI-NEXT:    s_mov_b32 s16, s7
-; SI-NEXT:    s_mov_b32 s18, s7
-; SI-NEXT:    s_mov_b32 s20, s7
-; SI-NEXT:    s_mov_b32 s23, s7
-; SI-NEXT:    s_mov_b32 s24, s7
-; SI-NEXT:    s_mov_b32 s26, s7
-; SI-NEXT:    s_mov_b32 s28, s7
-; SI-NEXT:    s_mov_b32 s30, s7
-; SI-NEXT:    s_mov_b32 s0, s4
-; SI-NEXT:    s_mov_b32 s1, s5
-; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s10
-; SI-NEXT:    v_alignbit_b32 v1, s11, v0, 24
-; SI-NEXT:    v_alignbit_b32 v0, s11, v0, 8
-; SI-NEXT:    s_lshr_b32 s6, s11, 24
-; SI-NEXT:    s_lshr_b32 s12, s11, 8
-; SI-NEXT:    s_lshl_b64 s[4:5], s[10:11], 8
-; SI-NEXT:    s_lshl_b64 s[32:33], s[10:11], 24
-; SI-NEXT:    s_lshl_b32 s19, s10, 24
-; SI-NEXT:    s_lshl_b32 s21, s10, 8
-; SI-NEXT:    v_mov_b32_e32 v2, s8
-; SI-NEXT:    v_alignbit_b32 v3, s9, v2, 24
-; SI-NEXT:    v_alignbit_b32 v2, s9, v2, 8
-; SI-NEXT:    s_lshr_b32 s32, s9, 8
-; SI-NEXT:    s_lshl_b64 s[10:11], s[8:9], 8
-; SI-NEXT:    s_and_b32 s15, s5, s25
-; SI-NEXT:    s_lshl_b64 s[4:5], s[8:9], 24
-; SI-NEXT:    s_lshl_b32 s29, s8, 24
-; SI-NEXT:    s_lshl_b32 s4, s8, 8
+; SI-NEXT:    s_mov_b32 s13, s11
+; SI-NEXT:    s_mov_b32 s14, s11
+; SI-NEXT:    s_mov_b32 s16, s11
+; SI-NEXT:    s_mov_b32 s18, s11
+; SI-NEXT:    s_mov_b32 s20, s11
+; SI-NEXT:    s_mov_b32 s23, s11
+; SI-NEXT:    s_mov_b32 s24, s11
+; SI-NEXT:    s_mov_b32 s26, s11
+; SI-NEXT:    s_mov_b32 s28, s11
+; SI-NEXT:    s_mov_b32 s30, s11
+; SI-NEXT:    s_mov_b32 s0, s8
+; SI-NEXT:    s_mov_b32 s1, s9
+; SI-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-NEXT:    v_mov_b32_e32 v0, s6
+; SI-NEXT:    v_alignbit_b32 v1, s7, v0, 24
+; SI-NEXT:    v_alignbit_b32 v0, s7, v0, 8
+; SI-NEXT:    s_lshr_b32 s10, s7, 24
+; SI-NEXT:    s_lshr_b32 s12, s7, 8
+; SI-NEXT:    s_lshl_b64 s[8:9], s[6:7], 8
+; SI-NEXT:    s_lshl_b64 s[32:33], s[6:7], 24
+; SI-NEXT:    s_lshl_b32 s19, s6, 24
+; SI-NEXT:    s_lshl_b32 s21, s6, 8
+; SI-NEXT:    v_mov_b32_e32 v2, s4
+; SI-NEXT:    v_alignbit_b32 v3, s5, v2, 24
+; SI-NEXT:    v_alignbit_b32 v2, s5, v2, 8
+; SI-NEXT:    s_lshr_b32 s32, s5, 8
+; SI-NEXT:    s_lshl_b64 s[6:7], s[4:5], 8
+; SI-NEXT:    s_and_b32 s15, s9, s25
+; SI-NEXT:    s_lshl_b64 s[8:9], s[4:5], 24
+; SI-NEXT:    s_lshl_b32 s29, s4, 24
+; SI-NEXT:    s_lshl_b32 s4, s4, 8
 ; SI-NEXT:    v_and_b32_e32 v1, s31, v1
 ; SI-NEXT:    v_and_b32_e32 v0, s22, v0
 ; SI-NEXT:    s_and_b32 s12, s12, s27
 ; SI-NEXT:    s_and_b32 s17, s33, s27
 ; SI-NEXT:    s_and_b32 s21, s21, s31
 ; SI-NEXT:    v_and_b32_e32 v3, s31, v3
 ; SI-NEXT:    v_and_b32_e32 v2, s22, v2
 ; SI-NEXT:    s_and_b32 s22, s32, s27
-; SI-NEXT:    s_and_b32 s25, s11, s25
-; SI-NEXT:    s_and_b32 s27, s5, s27
+; SI-NEXT:    s_and_b32 s25, s7, s25
+; SI-NEXT:    s_and_b32 s27, s9, s27
 ; SI-NEXT:    s_and_b32 s31, s4, s31
 ; SI-NEXT:    v_or_b32_e32 v0, v0, v1
-; SI-NEXT:    s_or_b64 s[4:5], s[12:13], s[6:7]
-; SI-NEXT:    s_or_b64 s[10:11], s[16:17], s[14:15]
+; SI-NEXT:    s_or_b64 s[6:7], s[12:13], s[10:11]
+; SI-NEXT:    s_or_b64 s[8:9], s[16:17], s[14:15]
 ; SI-NEXT:    s_or_b64 s[12:13], s[18:19], s[20:21]
 ; SI-NEXT:    v_or_b32_e32 v1, v2, v3
-; SI-NEXT:    s_lshr_b32 s6, s9, 24
-; SI-NEXT:    s_or_b64 s[8:9], s[26:27], s[24:25]
+; SI-NEXT:    s_lshr_b32 s10, s5, 24
+; SI-NEXT:    s_or_b64 s[4:5], s[26:27], s[24:25]
 ; SI-NEXT:    s_or_b64 s[14:15], s[28:29], s[30:31]
+; SI-NEXT:    v_or_b32_e32 v0, s6, v0
+; SI-NEXT:    v_mov_b32_e32 v3, s7
+; SI-NEXT:    s_or_b64 s[6:7], s[12:13], s[8:9]
+; SI-NEXT:    s_or_b64 s[8:9], s[22:23], s[10:11]
+; SI-NEXT:    s_or_b64 s[4:5], s[14:15], s[4:5]
+; SI-NEXT:    v_or_b32_e32 v2, s6, v0
+; SI-NEXT:    v_or_b32_e32 v3, s7, v3
+; SI-NEXT:    v_or_b32_e32 v0, s8, v1
+; SI-NEXT:    v_mov_b32_e32 v1, s9
 ; SI-NEXT:    v_or_b32_e32 v0, s4, v0
-; SI-NEXT:    v_mov_b32_e32 v3, s5
-; SI-NEXT:    s_or_b64 s[4:5], s[12:13], s[10:11]
-; SI-NEXT:    s_or_b64 s[6:7], s[22:23], s[6:7]
-; SI-NEXT:    s_or_b64 s[8:9], s[14:15], s[8:9]
-; SI-NEXT:    v_or_b32_e32 v2, s4, v0
-; SI-NEXT:    v_or_b32_e32 v3, s5, v3
-; SI-NEXT:    v_or_b32_e32 v0, s6, v1
-; SI-NEXT:    v_mov_b32_e32 v1, s7
-; SI-NEXT:    v_or_b32_e32 v0, s8, v0
-; SI-NEXT:    v_or_b32_e32 v1, s9, v1
+; SI-NEXT:    v_or_b32_e32 v1, s5, v1
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_bswap_v2i64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; VI-NEXT:    s_mov_b32 s9, 0
 ; VI-NEXT:    s_mov_b32 s14, 0xff0000

llvm/trunk/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir

+# RUN: llc -mtriple=amdgcn-- -run-pass=liveintervals,dead-mi-elimination,simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+
+# This is used to fail verififcation if MachineDCE tracks LIS.
+
+# GCN-LABEL: name: foo
+# GCN: S_ENDPGM
+---
+name:            foo
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+
+    %10:sreg_128 = S_LOAD_DWORDX4_IMM killed $noreg, 9, 0
+    S_NOP 0, implicit-def %4:sreg_128, implicit %10.sub1:sreg_128
+    S_CBRANCH_SCC0 %bb.3, implicit undef $scc
+    S_BRANCH %bb.1
+
+  bb.1:
+    S_CBRANCH_SCC0 %bb.2, implicit undef $scc
+    S_BRANCH %bb.3
+
+  bb.2:
+    %8:sreg_32_xm0 = COPY %4.sub1:sreg_128
+    %7:sreg_32_xm0 = COPY %10.sub1:sreg_128
+    S_BRANCH %bb.4
+
+  bb.3:
+    %10:sreg_128 = S_LOAD_DWORDX4_IMM killed $noreg, 10, 0
+    %7:sreg_32_xm0 = COPY %10.sub1:sreg_128
+    %8:sreg_32_xm0 = COPY %10.sub2:sreg_128
+
+  bb.4:
+    S_NOP 0, implicit %10
+    $sgpr0 = COPY %8:sreg_32_xm0
+    $sgpr1 = COPY %7:sreg_32_xm0
+    S_ENDPGM 0, implicit $sgpr0, implicit $sgpr1
+...

llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll

 ; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
 define amdgpu_cs float @ds_ordered_swap(i32 addrspace(2)* inreg %gds, i32 %value) {
   %val = call [e-mail](i32 addrspace(2)* %gds, i32 %value, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
   %r = bitcast i32 %val to float
   ret float %r
 }
 
 ; FUNC-LABEL: {{^}}ds_ordered_swap_conditional:
-; GCN: v_mov_b32_e32 v1, v0
-; GCN: v_cmp_ne_u32_e32 vcc, 0, v1
+; GCN: v_cmp_ne_u32_e32 vcc, 0, v0
 ; GCN: s_and_saveexec_b64 s[[SAVED:\[[0-9]+:[0-9]+\]]], vcc
 ; // We have to use s_cbranch, because ds_ordered_count has side effects with EXEC=0
 ; GCN: s_cbranch_execz [[BB:BB._.]]
 ; GCN: s_mov_b32 m0, s0
 ; VIGFX9-NEXT: s_nop 0
-; GCN-NEXT: ds_ordered_count v0, v1 offset:4868 gds
+; GCN-NEXT: ds_ordered_count v1, v0 offset:4868 gds
 ; GCN-NEXT: [[BB]]:
 ; // Wait for expcnt(0) before modifying EXEC
 ; GCN-NEXT: s_waitcnt expcnt(0)
 ; GCN-NEXT: s_or_b64 exec, exec, s[[SAVED]]
 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
 define amdgpu_cs float @ds_ordered_swap_conditional(i32 addrspace(2)* inreg %gds, i32 %value) {
 entry:
   %c = icmp ne i32 %value, 0