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[Sparc] Fix incorrect MI insertion position for spilling f128.
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Authored by Jim on Apr 8 2019, 12:40 AM.

Details

Summary

Obviously, new built MI (sethi+add or sethi+xor+add) for constructing large offset
should be inserted before new created MI for storing even register into memory.
So the insertion position should be *StMI instead of II.

before fixed:

std %f0, [%g1+80]
sethi 4, %g1 <<<
add %g1, %sp, %g1 <<< this two instructions should be put before "std %f0, [%g1+80]".
sethi 4, %g1
add %g1, %sp, %g1
std %f2, [%g1+88]

after fixed:

sethi 4, %g1
add %g1, %sp, %g1
std %f0, [%g1+80]
sethi 4, %g1
add %g1, %sp, %g1
std %f2, [%g1+88]

Diff Detail

Repository
rL LLVM

Event Timeline

Jim created this revision.Apr 8 2019, 12:40 AM
Jim edited the summary of this revision. (Show Details)Apr 8 2019, 12:40 AM

Can you please write a test case for this? There's some existing sparcv9 spill tests in llvm/test/CodeGen/SPARC/64spill.ll.

Jim updated this revision to Diff 194236.Apr 8 2019, 7:25 PM

Add test case for large stack offset.

jyknight accepted this revision.Apr 9 2019, 2:45 AM

Thanks!

This revision is now accepted and ready to land.Apr 9 2019, 2:45 AM
Jim edited the summary of this revision. (Show Details)Apr 9 2019, 3:40 AM
This revision was automatically updated to reflect the committed changes.