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Differential D60397

[Sparc] Fix incorrect MI insertion position for spilling f128.
ClosedPublic

Authored by Jim on Apr 8 2019, 12:40 AM.

Details

Reviewers
venkatra
jyknight
Commits
rG9a2cfaed4ebe: Merging r358042:
rL363010: Merging r358042:
rGa49c95e02aac: [Sparc] Fix incorrect MI insertion position for spilling f128.
rL358042: [Sparc] Fix incorrect MI insertion position for spilling f128.
Summary

Obviously, new built MI (sethi+add or sethi+xor+add) for constructing large offset
should be inserted before new created MI for storing even register into memory.
So the insertion position should be *StMI instead of II.

before fixed:

std %f0, [%g1+80]
sethi 4, %g1 <<<
add %g1, %sp, %g1 <<< this two instructions should be put before "std %f0, [%g1+80]".
sethi 4, %g1
add %g1, %sp, %g1
std %f2, [%g1+88]

after fixed:

sethi 4, %g1
add %g1, %sp, %g1
std %f0, [%g1+80]
sethi 4, %g1
add %g1, %sp, %g1
std %f2, [%g1+88]

Diff Detail

Repository
rL LLVM

Event Timeline

Jim created this revision.Apr 8 2019, 12:40 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 8 2019, 12:40 AM
Herald added subscribers: llvm-commits, jrtc27, fedor.sergeev, jyknight. · View Herald Transcript
Jim edited the summary of this revision. (Show Details)Apr 8 2019, 12:40 AM
Jim added a reviewer: jyknight.Apr 8 2019, 12:45 AM
jyknight added a comment.Apr 8 2019, 2:58 AM

Can you please write a test case for this? There's some existing sparcv9 spill tests in llvm/test/CodeGen/SPARC/64spill.ll.

Jim updated this revision to Diff 194236.Apr 8 2019, 7:25 PM

Add test case for large stack offset.

jyknight accepted this revision.Apr 9 2019, 2:45 AM

Thanks!

This revision is now accepted and ready to land.Apr 9 2019, 2:45 AM
Jim edited the summary of this revision. (Show Details)Apr 9 2019, 3:40 AM
Closed by commit rL358042: [Sparc] Fix incorrect MI insertion position for spilling f128. (authored by jimlin). · Explain WhyApr 9 2019, 6:55 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Sparc/
4 lines
test/
CodeGen/
SPARC/
23 lines

Diff 194436

llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp

Show First 20 Lines • Show All 182 Lines • ▼ Show 20 Lines if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
if (MI.getOpcode() == SP::STQFri) { if (MI.getOpcode() == SP::STQFri) {
const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
unsigned SrcReg = MI.getOperand(2).getReg(); unsigned SrcReg = MI.getOperand(2).getReg();
unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
MachineInstr *StMI = MachineInstr *StMI =
BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri)) BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
.addReg(FrameReg).addImm(0).addReg(SrcEvenReg); .addReg(FrameReg).addImm(0).addReg(SrcEvenReg);
replaceFI(MF, II, *StMI, dl, 0, Offset, FrameReg); replaceFI(MF, *StMI, *StMI, dl, 0, Offset, FrameReg);
MI.setDesc(TII.get(SP::STDFri)); MI.setDesc(TII.get(SP::STDFri));
MI.getOperand(2).setReg(SrcOddReg); MI.getOperand(2).setReg(SrcOddReg);
Offset += 8; Offset += 8;
} else if (MI.getOpcode() == SP::LDQFri) { } else if (MI.getOpcode() == SP::LDQFri) {
const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
unsigned DestReg = MI.getOperand(0).getReg(); unsigned DestReg = MI.getOperand(0).getReg();
unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64); unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
MachineInstr *StMI = MachineInstr *StMI =
BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg) BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
.addReg(FrameReg).addImm(0); .addReg(FrameReg).addImm(0);
replaceFI(MF, II, *StMI, dl, 1, Offset, FrameReg); replaceFI(MF, *StMI, *StMI, dl, 1, Offset, FrameReg);
MI.setDesc(TII.get(SP::LDDFri)); MI.setDesc(TII.get(SP::LDDFri));
MI.getOperand(0).setReg(DestOddReg); MI.getOperand(0).setReg(DestOddReg);
Offset += 8; Offset += 8;
} }
} }
replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg); replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg);
Show All 29 Lines

llvm/trunk/test/CodeGen/SPARC/fp128.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define void @f128_spill(fp128* noalias sret %scalar.result, fp128* byval %a) { define void @f128_spill(fp128* noalias sret %scalar.result, fp128* byval %a) {
entry: entry:
%0 = load fp128, fp128* %a, align 8 %0 = load fp128, fp128* %a, align 8
call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
store fp128 %0, fp128* %scalar.result, align 8 store fp128 %0, fp128* %scalar.result, align 8
ret void ret void
} }
; CHECK-LABEL: f128_spill_large:
; CHECK: sethi 4, %g1
; CHECK: sethi 4, %g1
; CHECK-NEXT: add %g1, %sp, %g1
; CHECK-NEXT: std %f{{.+}}, [%g1]
; CHECK: sethi 4, %g1
; CHECK-NEXT: add %g1, %sp, %g1
; CHECK-NEXT: std %f{{.+}}, [%g1+8]
; CHECK: sethi 4, %g1
; CHECK-NEXT: add %g1, %sp, %g1
; CHECK-NEXT: ldd [%g1], %f{{.+}}
; CHECK: sethi 4, %g1
; CHECK-NEXT: add %g1, %sp, %g1
; CHECK-NEXT: ldd [%g1+8], %f{{.+}}
define void @f128_spill_large(<251 x fp128>* noalias sret %scalar.result, <251 x fp128>* byval %a) {
entry:
%0 = load <251 x fp128>, <251 x fp128>* %a, align 8
call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
store <251 x fp128> %0, <251 x fp128>* %scalar.result, align 8
ret void
}
; CHECK-LABEL: f128_compare: ; CHECK-LABEL: f128_compare:
; HARD: fcmpq ; HARD: fcmpq
; HARD-NEXT: nop ; HARD-NEXT: nop
; SOFT: _Q_cmp ; SOFT: _Q_cmp
define i32 @f128_compare(fp128* byval %f0, fp128* byval %f1, i32 %a, i32 %b) { define i32 @f128_compare(fp128* byval %f0, fp128* byval %f1, i32 %a, i32 %b) {
entry: entry:
%0 = load fp128, fp128* %f0, align 8 %0 = load fp128, fp128* %f0, align 8
▲ Show 20 Lines • Show All 166 Lines • Show Last 20 Lines