[GlobalISel] Add a G_FPOWI instruction for @llvm.powi

[paquette]

Summary

Add an instruction to support @llvm.powi and add IRTranslator support for it.

Update arm64-irtranslator.ll and legalizer-info-validation.mir.

[paquette]

This landed forever ago

llvm/include/llvm/Support/TargetOpcodes.def

 HANDLE_TARGET_OPCODE(G_FDIV)
 
 /// Generic FP remainder.
 HANDLE_TARGET_OPCODE(G_FREM)
 
 /// Generic FP exponentiation.
 HANDLE_TARGET_OPCODE(G_FPOW)
 
+/// Generic FP exponentiation with integer power.
+HANDLE_TARGET_OPCODE(G_FPOWI)
+
 /// Generic base-e exponential of a value.
 HANDLE_TARGET_OPCODE(G_FEXP)
 
 /// Generic base-2 exponential of a value.
 HANDLE_TARGET_OPCODE(G_FEXP2)
 
 /// Floating point base-e logarithm of a value.
 HANDLE_TARGET_OPCODE(G_FLOG)

llvm/include/llvm/Target/GenericOpcodes.td

 
 // Floating point exponentiation.
 def G_FPOW : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src1, type0:$src2);
   let hasSideEffects = 0;
 }
 
+// Floating point exponentiation with integer power.
+def G_FPOWI : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1, type0:$src2);
+  let hasSideEffects = 0;
+}
+
 // Floating point base-e exponential of a value.
 def G_FEXP : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src1);
   let hasSideEffects = 0;
 }
 
 // Floating point base-2 exponential of a value.

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

switch (ID) {
     case Intrinsic::log:
       return TargetOpcode::G_FLOG;
     case Intrinsic::log2:
       return TargetOpcode::G_FLOG2;
     case Intrinsic::log10:
       return TargetOpcode::G_FLOG10;
     case Intrinsic::pow:
       return TargetOpcode::G_FPOW;
+    case Intrinsic::powi:
+      return TargetOpcode::G_FPOWI;
     case Intrinsic::round:
       return TargetOpcode::G_INTRINSIC_ROUND;
     case Intrinsic::sin:
       return TargetOpcode::G_FSIN;
     case Intrinsic::sqrt:
       return TargetOpcode::G_FSQRT;
     case Intrinsic::trunc:
       return TargetOpcode::G_INTRINSIC_TRUNC;

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

define void @test_stacksaverestore() {
   ; CHECK-LABEL: name: test_stacksaverestore
   ; CHECK: [[SAVE:%[0-9]+]]:_(p0) = COPY $sp
   ; CHECK-NEXT: $sp = COPY [[SAVE]](p0)
   ; CHECK-NEXT: RET_ReallyLR
   %sp = call i8* @llvm.stacksave()
   call void @llvm.stackrestore(i8* %sp)
   ret void
 }
+
+declare float @llvm.powi.f32(float, i32)
+define float @test_powi_intrin(float %l, i32 %r) {
+    ; CHECK-LABEL: name: test_powi_intrin
+    ; CHECK: [[REG1:%[0-9]+]]:_(s32) = COPY $s0
+    ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[REG3:%[0-9]+]]:_(s32) = G_FPOWI [[REG1]], [[REG2]]
+    ; CHECK-NEXT: $s0 = COPY [[REG3]](s32)
+  %res = call float @llvm.powi.f32(float %l, i32 %r)
+  ret float %res
+}

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

 # DEBUG:      .. the first uncovered type index: 1, OK
 #
 # DEBUG-NEXT: G_FREM (opcode {{[0-9]+}}): 1 type index
 # DEBUG:      .. the first uncovered type index: 1, OK
 #
 # DEBUG-NEXT: G_FPOW (opcode {{[0-9]+}}): 1 type index
 # DEBUG:      .. the first uncovered type index: 1, OK
 #
+# DEBUG-NEXT: G_FPOWI (opcode {{[0-9]+}}): 1 type index
+# DEBUG:      .. type index coverage check SKIPPED: no rules defined
+#
 # DEBUG-NEXT: G_FEXP (opcode {{[0-9]+}}): 1 type index
 # DEBUG:      .. the first uncovered type index: 1, OK
 #
 # DEBUG-NEXT: G_FEXP2 (opcode {{[0-9]+}}): 1 type index
 # DEBUG:      .. the first uncovered type index: 1, OK
 #
 # DEBUG-NEXT: G_FLOG (opcode {{[0-9]+}}): 1 type index
 # DEBUG:      .. the first uncovered type index: 1, OK