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Differential D60064

[AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructions
ClosedPublic

Authored by DavidSpickett on Apr 1 2019, 6:42 AM.

Details

Reviewers
javed.absar
Commits
rG9142b8ef1b9a: [AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructions
rL357395: [AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructions
Summary

The STGV/LDGV instructions were replaced with
STGM/LDGM. The encodings remain the same but there
is no longer writeback so there are no unpredictable
encodings to check for.

The specfication can be found here:
https://developer.arm.com/docs/ddi0596/c

Diff Detail

Event Timeline

DavidSpickett created this revision.Apr 1 2019, 6:42 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 1 2019, 6:42 AM
Herald added subscribers: llvm-commits, kristof.beyls, javed.absar. · View Herald Transcript
DavidSpickett added a reviewer: javed.absar.Apr 1 2019, 6:45 AM
javed.absar accepted this revision.Apr 1 2019, 7:22 AM
This revision is now accepted and ready to land.Apr 1 2019, 7:22 AM
Closed by commit rL357395: [AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructions (authored by DavidSpickett). · Explain WhyApr 1 2019, 7:51 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AArch64/
2 lines
11 lines
AsmParser/
9 lines
Disassembler/
27 lines
test/
MC/
AArch64/
65 lines
24 lines
Disassembler/
AArch64/
12 lines

Diff 193078

lib/Target/AArch64/AArch64InstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,018 Lines • ▼ Show 20 Linesclass BaseMemTag<bits<2> opc1, bits<2> opc2, string asm_insn,
let Inst{11-10} = opc2; let Inst{11-10} = opc2;
let Inst{9-5} = Rn; let Inst{9-5} = Rn;
// Inst{4-0} defined by subclass // Inst{4-0} defined by subclass
} }
class MemTagVector<bit Load, string asm_insn, string asm_opnds, class MemTagVector<bit Load, string asm_insn, string asm_opnds,
dag oops, dag iops> dag oops, dag iops>
: BaseMemTag<{0b1, Load}, 0b00, asm_insn, asm_opnds, : BaseMemTag<{0b1, Load}, 0b00, asm_insn, asm_opnds,
"$Rn = $wback,@earlyclobber $wback", oops, iops> { "", oops, iops> {
bits<5> Rt; bits<5> Rt;
let Inst{20-12} = 0b000000000; let Inst{20-12} = 0b000000000;
let Inst{4-0} = Rt; let Inst{4-0} = Rt;
let mayLoad = Load; let mayLoad = Load;
} }
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lib/Target/AArch64/AArch64InstrInfo.td

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Show First 20 Lines • Show All 1,250 Lines • ▼ Show 20 Linesdef SUBPS : SUBP<1, "subps", null_frag>, Sched<[]>{
let Defs = [NZCV]; let Defs = [NZCV];
} }
def : InstAlias<"cmpp $lhs, $rhs", (SUBPS XZR, GPR64sp:$lhs, GPR64sp:$rhs), 0>; def : InstAlias<"cmpp $lhs, $rhs", (SUBPS XZR, GPR64sp:$lhs, GPR64sp:$rhs), 0>;
def LDG : MemTagLoad<"ldg", "\t$Rt, [$Rn, $offset]">; def LDG : MemTagLoad<"ldg", "\t$Rt, [$Rn, $offset]">;
def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>; def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>;
def LDGV : MemTagVector<1, "ldgv", "\t$Rt, [$Rn]!", def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]",
(outs GPR64sp:$wback, GPR64:$Rt), (ins GPR64sp:$Rn)> { (outs GPR64:$Rt), (ins GPR64sp:$Rn)>;
let DecoderMethod = "DecodeLoadAllocTagArrayInstruction"; def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]",
} (outs), (ins GPR64:$Rt, GPR64sp:$Rn)>;
def STGV : MemTagVector<0, "stgv", "\t$Rt, [$Rn]!",
(outs GPR64sp:$wback), (ins GPR64:$Rt, GPR64sp:$Rn)>;
defm STG : MemTagStore<0b00, "stg">; defm STG : MemTagStore<0b00, "stg">;
defm STZG : MemTagStore<0b01, "stzg">; defm STZG : MemTagStore<0b01, "stzg">;
defm ST2G : MemTagStore<0b10, "st2g">; defm ST2G : MemTagStore<0b10, "st2g">;
defm STZ2G : MemTagStore<0b11, "stz2g">; defm STZ2G : MemTagStore<0b11, "stz2g">;
defm STGP : StorePairOffset <0b01, 0, GPR64z, simm7s16, "stgp">; defm STGP : StorePairOffset <0b01, 0, GPR64z, simm7s16, "stgp">;
def STGPpre : StorePairPreIdx <0b01, 0, GPR64z, simm7s16, "stgp">; def STGPpre : StorePairPreIdx <0b01, 0, GPR64z, simm7s16, "stgp">;
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lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Show First 20 Lines • Show All 4,090 Lines • ▼ Show 20 Lines case AArch64::STLXPX: {
unsigned Rt2 = Inst.getOperand(2).getReg(); unsigned Rt2 = Inst.getOperand(2).getReg();
unsigned Rn = Inst.getOperand(3).getReg(); unsigned Rn = Inst.getOperand(3).getReg();
if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) || if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) ||
(RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP)) (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
return Error(Loc[0], return Error(Loc[0],
"unpredictable STXP instruction, status is also a source"); "unpredictable STXP instruction, status is also a source");
break; break;
} }
case AArch64::LDGV: {
unsigned Rt = Inst.getOperand(0).getReg();
unsigned Rn = Inst.getOperand(1).getReg();
if (RI->isSubRegisterEq(Rt, Rn)) {
return Error(Loc[0],
"unpredictable LDGV instruction, writeback register is also "
"the target register");
}
}
} }
// Now check immediate ranges. Separate from the above as there is overlap // Now check immediate ranges. Separate from the above as there is overlap
// in the instructions being checked and this keeps the nested conditionals // in the instructions being checked and this keeps the nested conditionals
// to a minimum. // to a minimum.
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case AArch64::ADDSWri: case AArch64::ADDSWri:
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lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

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static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
template <int ElementWidth> template <int ElementWidth>
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
uint64_t Addr, const void *Decoder); uint64_t Addr, const void *Decoder);
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
uint64_t Addr, const void *Decoder); uint64_t Addr, const void *Decoder);
static DecodeStatus DecodeLoadAllocTagArrayInstruction(MCInst &Inst,
uint32_t insn,
uint64_t address,
const void* Decoder);
static bool Check(DecodeStatus &Out, DecodeStatus In) { static bool Check(DecodeStatus &Out, DecodeStatus In) {
switch (In) { switch (In) {
case MCDisassembler::Success: case MCDisassembler::Success:
// Out stays the same. // Out stays the same.
return true; return true;
case MCDisassembler::SoftFail: case MCDisassembler::SoftFail:
Out = In; Out = In;
return true; return true;
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} }
// Decode uimm4 ranged from 1-16. // Decode uimm4 ranged from 1-16.
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
uint64_t Addr, const void *Decoder) { uint64_t Addr, const void *Decoder) {
Inst.addOperand(MCOperand::createImm(Imm + 1)); Inst.addOperand(MCOperand::createImm(Imm + 1));
return Success; return Success;
} }
static DecodeStatus DecodeLoadAllocTagArrayInstruction(MCInst &Inst,
uint32_t insn,
uint64_t address,
const void* Decoder) {
unsigned Rn = fieldFromInstruction(insn, 5, 5);
unsigned Rt = fieldFromInstruction(insn, 0, 5);
// Outputs
DecodeGPR64spRegisterClass(Inst, Rn, address, Decoder);
DecodeGPR64RegisterClass(Inst, Rt, address, Decoder);
// Input (Rn again)
Inst.addOperand(Inst.getOperand(0));
//Do this post decode since the raw number for xzr and sp is the same
if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
return SoftFail;
} else {
return Success;
}
}

test/MC/AArch64/armv8.5a-mte-error.s

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// CHECK-NEXT: ldg x0 // CHECK-NEXT: ldg x0
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: ldg x0, [#0] // CHECK-NEXT: ldg x0, [#0]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: ldg w0, [x1] // CHECK-NEXT: ldg w0, [x1]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: ldg x0, [w1] // CHECK-NEXT: ldg x0, [w1]
ldgv ldgm
ldgv x0 ldgm x0
ldgv x0, [x1] ldgm w0, [x1]
ldgv sp, [x0]! ldgm x0, [w1]
ldgv x3, [x3]! ldgm #1, [x1]
ldgv w0, [x1]! ldgm x0, [#1]
ldgv x0, [w1]! ldgm sp, [x0]
ldgv #1, [x1]!
ldgv x0, [#1]!
// CHECK: too few operands for instruction // CHECK: too few operands for instruction
// CHECK-NEXT: ldgv // CHECK-NEXT: ldgm
// CHECK: too few operands for instruction // CHECK: too few operands for instruction
// CHECK-NEXT: ldgv x0 // CHECK-NEXT: ldgm x0
// CHECK: too few operands for instruction
// CHECK-NEXT: ldgv x0, [x1]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: ldgv sp, [x0]! // CHECK-NEXT: ldgm w0, [x1]
// CHECK: unpredictable LDGV instruction, writeback register is also the target register
// CHECK-NEXT: ldgv x3, [x3]!
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: ldgv w0, [x1]! // CHECK-NEXT: ldgm x0, [w1]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: ldgv x0, [w1]! // CHECK-NEXT: ldgm #1, [x1]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: ldgv #1, [x1]! // CHECK-NEXT: ldgm x0, [#1]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: ldgv x0, [#1]! // CHECK-NEXT: ldgm sp, [x0]
stgv stgm
stgv x0 stgm x0
stgv x0, [x1] stgm sp, [x0]
stgv sp, [x0]! stgm w0, [x0]
stgv w0, [x0]! stgm x0, [w0]
stgv x0, [w0]! stgm #1, [x1]
stgv #1, [x1]! stgm x0, [#1]
stgv x0, [#1]!
// CHECK: too few operands for instruction // CHECK: too few operands for instruction
// CHECK-NEXT: stgv // CHECK-NEXT: stgm
// CHECK: too few operands for instruction
// CHECK-NEXT: stgv x0
// CHECK: too few operands for instruction // CHECK: too few operands for instruction
// CHECK-NEXT: stgv x0, [x1] // CHECK-NEXT: stgm x0
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stgv sp, [x0]! // CHECK-NEXT: stgm sp, [x0]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stgv w0, [x0]! // CHECK-NEXT: stgm w0, [x0]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stgv x0, [w0]! // CHECK-NEXT: stgm x0, [w0]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stgv #1, [x1]! // CHECK-NEXT: stgm #1, [x1]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stgv x0, [#1]! // CHECK-NEXT: stgm x0, [#1]

test/MC/AArch64/armv8.5a-mte.s

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// CHECK: ldg x0, [x1] // encoding: [0x20,0x00,0x60,0xd9] // CHECK: ldg x0, [x1] // encoding: [0x20,0x00,0x60,0xd9]
// CHECK: ldg x2, [sp, #-4096] // encoding: [0xe2,0x03,0x70,0xd9] // CHECK: ldg x2, [sp, #-4096] // encoding: [0xe2,0x03,0x70,0xd9]
// CHECK: ldg x3, [x4, #4080] // encoding: [0x83,0xf0,0x6f,0xd9] // CHECK: ldg x3, [x4, #4080] // encoding: [0x83,0xf0,0x6f,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
ldgv x0, [x1]! ldgm x0, [x1]
ldgv x1, [sp]! ldgm x1, [sp]
ldgv xzr, [x2]! ldgm xzr, [x2]
// CHECK: ldgv x0, [x1]! // encoding: [0x20,0x00,0xe0,0xd9] // CHECK: ldgm x0, [x1] // encoding: [0x20,0x00,0xe0,0xd9]
// CHECK: ldgv x1, [sp]! // encoding: [0xe1,0x03,0xe0,0xd9] // CHECK: ldgm x1, [sp] // encoding: [0xe1,0x03,0xe0,0xd9]
// CHECK: ldgv xzr, [x2]! // encoding: [0x5f,0x00,0xe0,0xd9] // CHECK: ldgm xzr, [x2] // encoding: [0x5f,0x00,0xe0,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
stgv x0, [x1]! stgm x0, [x1]
stgv x1, [sp]! stgm x1, [sp]
stgv xzr, [x2]! stgm xzr, [x2]
// CHECK: stgv x0, [x1]! // encoding: [0x20,0x00,0xa0,0xd9] // CHECK: stgm x0, [x1] // encoding: [0x20,0x00,0xa0,0xd9]
// CHECK: stgv x1, [sp]! // encoding: [0xe1,0x03,0xa0,0xd9] // CHECK: stgm x1, [sp] // encoding: [0xe1,0x03,0xa0,0xd9]
// CHECK: stgv xzr, [x2]! // encoding: [0x5f,0x00,0xa0,0xd9] // CHECK: stgm xzr, [x2] // encoding: [0x5f,0x00,0xa0,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte

test/MC/Disassembler/AArch64/armv8.5a-mte-unpredictable.txt

  • This file was deleted.
# RUN: llvm-mc -triple=aarch64 -mattr=+mte -disassemble < %s 2>&1 | FileCheck %s
# ldgv x1, [x1]!
[0x21,0x00,0xe0,0xd9]
# CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: [0x21,0x00,0xe0,0xd9]

test/MC/Disassembler/AArch64/armv8.5a-mte.txt

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[0x20,0x00,0xe0,0xd9] [0x20,0x00,0xe0,0xd9]
[0xe1,0x03,0xe0,0xd9] [0xe1,0x03,0xe0,0xd9]
[0x5f,0x00,0xe0,0xd9] [0x5f,0x00,0xe0,0xd9]
[0x20,0x00,0xa0,0xd9] [0x20,0x00,0xa0,0xd9]
[0xe1,0x03,0xa0,0xd9] [0xe1,0x03,0xa0,0xd9]
[0x5f,0x00,0xa0,0xd9] [0x5f,0x00,0xa0,0xd9]
# CHECK: ldgv x0, [x1]! # CHECK: ldgm x0, [x1]
# CHECK: ldgv x1, [sp]! # CHECK: ldgm x1, [sp]
# CHECK: ldgv xzr, [x2]! # CHECK: ldgm xzr, [x2]
# CHECK: stgv x0, [x1]! # CHECK: stgm x0, [x1]
# CHECK: stgv x1, [sp]! # CHECK: stgm x1, [sp]
# CHECK: stgv xzr, [x2]! # CHECK: stgm xzr, [x2]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x20,0x00,0xe0,0xd9] # NOMTE-NEXT: [0x20,0x00,0xe0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xe1,0x03,0xe0,0xd9] # NOMTE-NEXT: [0xe1,0x03,0xe0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0x00,0xe0,0xd9] # NOMTE-NEXT: [0x5f,0x00,0xe0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
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test/MC/AArch64/armv8.5a-mte.s