[AArch64][SVE] Asm: error on unexpected SVE vector register type suffix

[c-rhodes]

Summary

This patch fixes an assembler bug that allowed SVE vector registers to contain a
type suffix when not expected. The SVE unpredicated movprfx instruction is the
only instruction affected.

The following are examples of what was previously valid:

movprfx z0.b, z0.b
movprfx z0.b, z0.s
movprfx z0, z0.s

These instructions are now erroneous.

[sdesmalen]

Thanks @c-rhodes, this was indeed a mismatch with the SVE spec. Minor nit: the SVE spill/fill instructions also take ZPRAny operands, you could add some tests for those instructions as well to ensure it is not limited to movprfx alone.

[c-rhodes]

@sdesmalen np, I'll add tests for those instructions also.

[c-rhodes]

• Fixed a typo in an error message.
• Added further tests for LDR/STR for full coverage on instructions using ZPRAny.
• Added another small testcase to movprfx to test type suffix only on the last vector register.

[sdesmalen]

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

1093 ↗

(On Diff #192059)

nit: unnecessary parentheses around Reg.ElementWidth == ElementWidth

[c-rhodes]

Removed unnecessary parenthesis.

[sdesmalen]

Thanks @c-rhodes, LGTM.

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

     if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
       return DiagnosticPredicateTy::NoMatch;
 
-    if (isSVEVectorReg<Class>() &&
-           (ElementWidth == 0 || Reg.ElementWidth == ElementWidth))
+    if (isSVEVectorReg<Class>() && (Reg.ElementWidth == ElementWidth))
       return DiagnosticPredicateTy::Match;
 
     return DiagnosticPredicateTy::NearMatch;

llvm/test/MC/AArch64/SVE/movprfx-diagnostics.s

 // RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve  2>&1 < %s | FileCheck %s
 
 // ------------------------------------------------------------------------- //
+// Type suffix on unpredicated movprfx
+
+movprfx z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: movprfx z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.b, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: movprfx z0.b, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Different destination register (unary)
 
 movprfx z0, z1