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[AArch64][GlobalISel] Add an optimization to select vector DUP instructions
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Authored by aemerson on Mar 19 2019, 1:28 PM.

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Summary

This adds pattern matching for the insert+shufflevector sequence so we can generate dup instructions instead of the current TBL sequence.

Currently doesn't handle vectors < 128b in size yet.

Diff Detail

Repository
rL LLVM

Event Timeline

aemerson created this revision.Mar 19 2019, 1:28 PM
paquette accepted this revision.Mar 19 2019, 1:44 PM

LGTM.

Some minor nits included.

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
2354 ↗(On Diff #191382)

Maybe include what we're transforming it into here?

2387 ↗(On Diff #191382)

for (unsigned i = 1, e = ZeroVec->getNumOperands() - 1; i < e; ++i) ?

2396 ↗(On Diff #191382)

Maybe some debug output here or a TODO or something?

2420 ↗(On Diff #191382)

This logic can probably be tightened a bit?

This revision is now accepted and ready to land.Mar 19 2019, 1:44 PM
This revision was automatically updated to reflect the committed changes.