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[TargetLowering] Add SimplifyDemandedBits support for ISD::INSERT_VECTOR_ELT
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Authored by RKSimon on Mar 18 2019, 5:38 AM.

Details

Summary

This helps us relax the extension of a lot of scalar elements before they are inserted into a vector.

Its exposes an issue in DAGCombiner::convertBuildVecZextToZext as some/all the zero-extensions may be relaxed to ANY_EXTEND, so we need to handle that case to avoid a couple of AVX2 VPMOVZX test regressions.

Once this is in it should be easier to fix a number of remaining failures to fold loads into VBROADCAST nodes.

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rL LLVM

Event Timeline

RKSimon created this revision.Mar 18 2019, 5:38 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 18 2019, 5:38 AM
nikic added inline comments.Mar 24 2019, 1:49 PM
lib/CodeGen/SelectionDAG/TargetLowering.cpp
578

Why is this check necessary? If there are no demanded elements, wouldn't this allow folding the input vector to undef?

RKSimon updated this revision to Diff 192047.Mar 24 2019, 3:43 PM

Always call SimplifyDemandedBits on the base vector to force to UNDEF - I wasn't doing this beforehand to try and avoid losing KnownBits info but we can just ignore the KnownBits from the base vector if its not actually demanded.

nikic accepted this revision.Mar 25 2019, 1:40 PM

LGTM

This revision is now accepted and ready to land.Mar 25 2019, 1:40 PM
This revision was automatically updated to reflect the committed changes.