CodeGenPrepare: preserve inbounds attribute when sinking GEPs

[t.p.northover]

Summary

This is part of the groundwork for supporting the AArch64 ILP32 ABI.

Targets can potentially emit more efficient code if they know address computations never overflow. For example ILP32 code on AArch64 (which only has 64-bit address computation) can ignore the possibility of overflow with this extra information.

[dmgreen]

This looks generally useful. Please add context

llvm/lib/CodeGen/CodeGenPrepare.cpp

1954

This can perhaps go with the other variables above the enum

1975

If one of the two is inbounds, does that not make the other inbounds? In other words, why would a mismatch in the inbounds flag matter?

2077

I would drop the brackets, but it's only debug output so up to you.

llvm/test/CodeGen/Thumb/addr-modes.ll

37

This isn't really inbounds, is it? But we don't use that info here, (we don't create a gep), so it's alright? It's a little confusing, at least

[t.p.northover]

Please add context

Very sorry about that. I used git format-patch and I don't have the -U9999 muscle memory there. Updated patch should have it.

llvm/lib/CodeGen/CodeGenPrepare.cpp

1975

A violation would mean that one of the instructions produces undef and the other produces a known result, so I believe we could combine them by stripping off the inbounds attribute on the merged instruction.

But personally I doubt it's worth the effort. As far as I know, front-ends don't actually mix the two (all C and C++ arithmetic is inbounds or via inttoptr/ptrtoint).

2077

I can replace them by a space, which looks a bit more natural. We don't want it running into the following stuff.

llvm/test/CodeGen/Thumb/addr-modes.ll

37

I think you were right to be suspicious, it could theoretically be turned into a GEP i16, null, %x or something and the tag would be wrong there. I've fixed it in the updated patch.

[dmgreen]

Looks good to me then.

llvm/lib/CodeGen/CodeGenPrepare.cpp

1975

I thought (correct me if I'm wrong) that a violation would produce poison. And because we know the results are used in a load/store, that would be UB. So we can presume that doesn't happen, and having inbounds on one implies inbounds on the other, providing they are otherwise identical.

I did see one example of this making a difference, although it was rather complex, quite a small change (and more often went up, not down). You are probably correct about it not being worth the effort.

[t.p.northover]

llvm/lib/CodeGen/CodeGenPrepare.cpp

1975

I thought (correct me if I'm wrong) that a violation would produce poison

Sorry, yes.

And because we know the results are used in a load/store, that would be UB. So we can presume that doesn't happen, and having inbounds on one implies inbounds on the other.

I think we (may) know it's statically used, but there could still be a dynamic check that makes the inbounds poison innocuous but would cause bad things if the wrapping GEP suddenly became inbounds.

[dmgreen]

llvm/lib/CodeGen/CodeGenPrepare.cpp

1975

Yeah, I agree. Should rarely come up, and more trouble than it's worth.

[t.p.northover]

Thanks for the review. Committed as r355926.

llvm/lib/CodeGen/CodeGenPrepare.cpp

 /// bb0:
 ///   %tmp0 = tail call i32 @f0()
 ///   ret i32 %tmp0
 /// bb1:
 ///   %tmp1 = tail call i32 @f1()
 ///   ret i32 %tmp1
 /// bb2:
 ///   %tmp2 = tail call i32 @f2()
 ///   ret i32 %tmp2
 /// @endcode
 bool CodeGenPrepare::dupRetToEnableTailCallOpts(BasicBlock *BB) {
   if (!TLI)
     return false;
 
   ReturnInst *RetI = dyn_cast<ReturnInst>(BB->getTerminator());
   if (!RetI)
     return false;
 
   PHINode *PN = nullptr;
   BitCastInst *BCI = nullptr;
   Value *V = RetI->getReturnValue();
   if (V) {
     BCI = dyn_cast<BitCastInst>(V);
     if (BCI)
       V = BCI->getOperand(0);
 
     PN = dyn_cast<PHINode>(V);
     if (!PN)
       return false;
   }
 
   if (PN && PN->getParent() != BB)
     return false;
 
   // Make sure there are no instructions between the PHI and return, or that the
   // return is the first instruction in the block.
   if (PN) {
     BasicBlock::iterator BI = BB->begin();

 namespace {
 
 /// This is an extended version of TargetLowering::AddrMode
 /// which holds actual Value*'s for register values.
 struct ExtAddrMode : public TargetLowering::AddrMode {
   Value *BaseReg = nullptr;
   Value *ScaledReg = nullptr;
   Value *OriginalValue = nullptr;
+  bool InBounds = true;
 
   enum FieldName {
     NoField        = 0x00,
     BaseRegField   = 0x01,
     BaseGVField    = 0x02,
     BaseOffsField  = 0x04,
     ScaledRegField = 0x08,
     ScaleField     = 0x10,
     MultipleFields = 0xff
   };
 
+
   ExtAddrMode() = default;
 
   void print(raw_ostream &OS) const;
   void dump() const;
 
   FieldName compare(const ExtAddrMode &other) {
     // First check that the types are the same on each field, as differing types
     // is something we can't cope with later on.
     if (BaseReg && other.BaseReg &&
         BaseReg->getType() != other.BaseReg->getType())
       return MultipleFields;
     if (BaseGV && other.BaseGV &&
         BaseGV->getType() != other.BaseGV->getType())
       return MultipleFields;
     if (ScaledReg && other.ScaledReg &&
         ScaledReg->getType() != other.ScaledReg->getType())
       return MultipleFields;
 
+    // Conservatively reject 'inbounds' mismatches.
+    if (InBounds != other.InBounds)
+      return MultipleFields;
+
     // Check each field to see if it differs.
     unsigned Result = NoField;
     if (BaseReg != other.BaseReg)
       Result |= BaseRegField;
     if (BaseGV != other.BaseGV)
       Result |= BaseGVField;
     if (BaseOffs != other.BaseOffs)
       Result |= BaseOffsField;
static inline raw_ostream &operator<<(raw_ostream &OS, const ExtAddrMode &AM) {
   return OS;
 }
 #endif
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 void ExtAddrMode::print(raw_ostream &OS) const {
   bool NeedPlus = false;
   OS << "[";
+  if (InBounds)
+    OS << "inbounds ";
   if (BaseGV) {
     OS << (NeedPlus ? " + " : "")
        << "GV:";
     BaseGV->printAsOperand(OS, /*PrintType=*/false);
     NeedPlus = true;
   }
 
   if (BaseOffs) {
bool AddressingModeMatcher::matchScaledValue(Value *ScaleReg, int64_t Scale,
   AddrMode = TestAddrMode;
 
   // Okay, we decided that we can add ScaleReg+Scale to AddrMode.  Check now
   // to see if ScaleReg is actually X+C.  If so, we can turn this into adding
   // X*Scale + C*Scale to addr mode.
   ConstantInt *CI = nullptr; Value *AddLHS = nullptr;
   if (isa<Instruction>(ScaleReg) &&  // not a constant expr.
       match(ScaleReg, m_Add(m_Value(AddLHS), m_ConstantInt(CI)))) {
+    TestAddrMode.InBounds = false;
     TestAddrMode.ScaledReg = AddLHS;
     TestAddrMode.BaseOffs += CI->getSExtValue()*TestAddrMode.Scale;
 
     // If this addressing mode is legal, commit it and remember that we folded
     // this instruction.
     if (TLI.isLegalAddressingMode(DL, TestAddrMode, AccessTy, AddrSpace)) {
       AddrModeInsts.push_back(cast<Instruction>(ScaleReg));
       AddrMode = TestAddrMode;
case Instruction::Add: {
     unsigned OldSize = AddrModeInsts.size();
     // Start a transaction at this point.
     // The LHS may match but not the RHS.
     // Therefore, we need a higher level restoration point to undo partially
     // matched operation.
     TypePromotionTransaction::ConstRestorationPt LastKnownGood =
         TPT.getRestorationPoint();
 
+    AddrMode.InBounds = false;
     if (matchAddr(AddrInst->getOperand(1), Depth+1) &&
         matchAddr(AddrInst->getOperand(0), Depth+1))
       return true;
 
     // Restore the old addr mode info.
     AddrMode = BackupAddrMode;
     AddrModeInsts.resize(OldSize);
     TPT.rollback(LastKnownGood);
case Instruction::Add: {
     break;
   }
   //case Instruction::Or:
   // TODO: We can handle "Or Val, Imm" iff this OR is equivalent to an ADD.
   //break;
   case Instruction::Mul:
   case Instruction::Shl: {
     // Can only handle X*C and X << C.
+    AddrMode.InBounds = false;
     ConstantInt *RHS = dyn_cast<ConstantInt>(AddrInst->getOperand(1));
     if (!RHS || RHS->getBitWidth() > 64)
       return false;
     int64_t Scale = RHS->getSExtValue();
     if (Opcode == Instruction::Shl)
       Scale = 1LL << Scale;
 
     return matchScaledValue(AddrInst->getOperand(0), Scale, Depth);
case Instruction::GetElementPtr: {
 
     // A common case is for the GEP to only do a constant offset.  In this case,
     // just add it to the disp field and check validity.
     if (VariableOperand == -1) {
       AddrMode.BaseOffs += ConstantOffset;
       if (ConstantOffset == 0 ||
           TLI.isLegalAddressingMode(DL, AddrMode, AccessTy, AddrSpace)) {
         // Check to see if we can fold the base pointer in too.
-        if (matchAddr(AddrInst->getOperand(0), Depth+1))
+        if (matchAddr(AddrInst->getOperand(0), Depth+1)) {
+          if (!cast<GEPOperator>(AddrInst)->isInBounds())
+            AddrMode.InBounds = false;
           return true;
+        }
       } else if (EnableGEPOffsetSplit && isa<GetElementPtrInst>(AddrInst) &&
                  TLI.shouldConsiderGEPOffsetSplit() && Depth == 0 &&
                  ConstantOffset > 0) {
         // Record GEPs with non-zero offsets as candidates for splitting in the
         // event that the offset cannot fit into the r+i addressing mode.
         // Simple and common case that only one GEP is used in calculating the
         // address for the memory access.
         Value *Base = AddrInst->getOperand(0);
case Instruction::GetElementPtr: {
     }
 
     // Save the valid addressing mode in case we can't match.
     ExtAddrMode BackupAddrMode = AddrMode;
     unsigned OldSize = AddrModeInsts.size();
 
     // See if the scale and offset amount is valid for this target.
     AddrMode.BaseOffs += ConstantOffset;
+    if (!cast<GEPOperator>(AddrInst)->isInBounds())
+      AddrMode.InBounds = false;
 
     // Match the base operand of the GEP.
     if (!matchAddr(AddrInst->getOperand(0), Depth+1)) {
       // If it couldn't be matched, just stuff the value in a register.
       if (AddrMode.HasBaseReg) {
         AddrMode = BackupAddrMode;
         AddrModeInsts.resize(OldSize);
         return false;
if (!ResultPtr &&
       // Add in the Base Offset if present.
       if (AddrMode.BaseOffs) {
         Value *V = ConstantInt::get(IntPtrTy, AddrMode.BaseOffs);
         if (ResultIndex) {
           // We need to add this separately from the scale above to help with
           // SDAG consecutive load/store merging.
           if (ResultPtr->getType() != I8PtrTy)
             ResultPtr = Builder.CreatePointerCast(ResultPtr, I8PtrTy);
-          ResultPtr = Builder.CreateGEP(I8Ty, ResultPtr, ResultIndex, "sunkaddr");
+          ResultPtr =
+              AddrMode.InBounds
+                  ? Builder.CreateInBoundsGEP(I8Ty, ResultPtr, ResultIndex,
+                                              "sunkaddr")
+                  : Builder.CreateGEP(I8Ty, ResultPtr, ResultIndex, "sunkaddr");
         }
 
         ResultIndex = V;
       }
 
       if (!ResultIndex) {
         SunkAddr = ResultPtr;
       } else {
         if (ResultPtr->getType() != I8PtrTy)
           ResultPtr = Builder.CreatePointerCast(ResultPtr, I8PtrTy);
-        SunkAddr = Builder.CreateGEP(I8Ty, ResultPtr, ResultIndex, "sunkaddr");
+        SunkAddr =
+            AddrMode.InBounds
+                ? Builder.CreateInBoundsGEP(I8Ty, ResultPtr, ResultIndex,
+                                            "sunkaddr")
+                : Builder.CreateGEP(I8Ty, ResultPtr, ResultIndex, "sunkaddr");
       }
 
       if (SunkAddr->getType() != Addr->getType())
         SunkAddr = Builder.CreatePointerCast(SunkAddr, Addr->getType());
     }
   } else {
     // We'd require a ptrtoint/inttoptr down the line, which we can't do for
     // non-integral pointers, so in that case bail out now.

llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll

 
 done:
   ret void
 }
 
 %struct.foo = type { [3 x float], [3 x float] }
 
 ; OPT-LABEL: @sink_ds_address(
-; OPT: getelementptr i8,
+; OPT: getelementptr inbounds i8,
 
 ; GCN-LABEL: {{^}}sink_ds_address:
 ; GCN: s_load_dword [[SREG1:s[0-9]+]],
 ; GCN: v_mov_b32_e32 [[VREG1:v[0-9]+]], [[SREG1]]
 ; GCN-DAG: ds_read2_b32 v[{{[0-9+:[0-9]+}}], [[VREG1]] offset0:3 offset1:5
 define amdgpu_kernel void @sink_ds_address(%struct.foo addrspace(3)* nocapture %ptr) nounwind {
 entry:
   %x = getelementptr inbounds %struct.foo, %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 0

llvm/test/CodeGen/Thumb/addr-modes.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -debug-only=codegenprepare -o /dev/null 2>&1 | FileCheck %s
 
 ; These are regression tests for
 ;  https://bugs.llvm.org/show_bug.cgi?id=34106
 ;    "ARMTargetLowering::isLegalAddressingMode can accept incorrect
 ;    addressing modes for Thumb1 target"
 ;
 ; The Thumb1 target addressing modes don't support scaling.
 ; It supports: r1 + r2, where r1 and r2 can be the same register.
 
 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
 target triple = "thumbv6m-arm-none-eabi"
 
 ; Test case 01: %n is scaled by 4 (size of i32).
 ; Expected: GEP cannot be folded into LOAD.
-; CHECK: local addrmode: [Base:%arrayidx]
+; CHECK: local addrmode: [inbounds Base:%arrayidx]
 define i32 @load01(i32* %p, i32 %n) nounwind {
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %p, i32 %n
   %0 = load i32, i32* %arrayidx, align 4
   ret i32 %0
 }
 
 ; Test case 02: No scale of %n is needed because the size of i8 is 1.
 ; Expected: GEP can be folded into LOAD.
-; CHECK: local addrmode: [Base:%p + 1*%n]
+; CHECK: local addrmode: [inbounds Base:%p + 1*%n]
 define i8 @load02(i8* %p, i32 %n) nounwind {
 entry:
   %arrayidx = getelementptr inbounds i8, i8* %p, i32 %n
   %0 = load i8, i8* %arrayidx
   ret i8 %0
 }
 
 ; Test case 03: 2*%x can be represented as %x + %x.
 ; Expected: GEP can be folded into LOAD.
 ; CHECK: local addrmode: [2*%x]
 define i32 @load03(i32 %x) nounwind {
 entry:
   %mul = shl nsw i32 %x, 1
   %0 = inttoptr i32 %mul to i32*
   %1 = load i32, i32* %0, align 4
   ret i32 %1
 }
 

llvm/test/Transforms/CodeGenPrepare/Mips/pr35209.ll

 ; CHECK: %[[I0:[0-9]+]] = load %struct.az*, %struct.az** @j
 ; CHECK-LABEL: cl:
 
 ; CHECK-NOT: %{{[0-9]+}}  = load %struct.bt*, %struct.bt** %bw
 ; CHECK-NOT: %{{[.a-z0-9]}} = select
 ; CHECK-NOT: %{{[0-9]+}}  = load %struct.bt*, %struct.bt** %bw
 
 ; CHECK: %[[I1:[0-9]+]] = bitcast %struct.az* %[[I0]] to i8*
-; CHECK-NEXT: %sunkaddr = getelementptr i8, i8* %[[I1]], i64 8
+; CHECK-NEXT: %sunkaddr = getelementptr inbounds i8, i8* %[[I1]], i64 8
 ; CHECK-NEXT: %[[I2:[0-9]+]] = bitcast i8* %sunkaddr to %struct.bt**
 ; CHECK-NEXT: %{{[0-9]+}} = load %struct.bt*, %struct.bt** %[[I2]]
 ; CHECK-NEXT: tail call void (i8*, ...) @a
 
 declare inreg { i64, i64 } @ba(i32*)
 
 declare void @a(i8*, ...)

llvm/test/Transforms/CodeGenPrepare/X86/computedgoto.ll

 ; CHECK:       bb0:
 ; CHECK-NEXT:    tail call void @use(i32 0)
 ; CHECK-NEXT:    br label [[INDIRECTGOTO:%.*]]
 ; CHECK:       bb1:
 ; CHECK-NEXT:    tail call void @use(i32 1)
 ; CHECK-NEXT:    br label [[INDIRECTGOTO]]
 ; CHECK:       indirectgoto:
 ; CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32* [[P]] to i8*
-; CHECK-NEXT:    [[SUNKADDR:%.*]] = getelementptr i8, i8* [[TMP0]], i64 4
+; CHECK-NEXT:    [[SUNKADDR:%.*]] = getelementptr inbounds i8, i8* [[TMP0]], i64 4
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[SUNKADDR]] to i32*
 ; CHECK-NEXT:    [[NEWP:%.*]] = load i32, i32* [[TMP1]], align 4
 ; CHECK-NEXT:    [[IDX:%.*]] = sext i32 [[NEWP]] to i64
 ; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* @nophi.targets, i64 0, i64 [[IDX]]
 ; CHECK-NEXT:    [[NEWOP:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8
 ; CHECK-NEXT:    indirectbr i8* [[NEWOP]], [label [[BB0]], label %bb1]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret void

llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll

entry:
   br i1 %cond, label %if.then, label %fallthrough
 
 if.then:
   %a2 = getelementptr inbounds i64, i64* %b2, i64 5
   %c2 = bitcast i64* %a2 to i32*
   br label %fallthrough
 
 fallthrough:
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
   %b = phi i64* [%b1, %entry], [%b2, %if.then]
   %c = phi i32* [%c1, %entry], [%c2, %if.then]
   %v = load i32, i32* %c, align 4
   ret i32 %v
 }
 
 ; Can we sink for different base if there is phi for base but not valid one?
 define i32 @test3(i1 %cond, i64* %b1, i64* %b2) {
entry:
   %a2 = getelementptr inbounds i64, i64* %b2, i64 5
   %c2 = bitcast i64* %a2 to i32*
   br i1 %cond, label %if.then, label %fallthrough
 
 if.then:
   br label %fallthrough
 
 fallthrough:
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
   %b = phi i64* [%b1, %entry], [%b2, %if.then]
   %c = phi i32* [%c1, %entry], [%c2, %if.then]
   %v = load i32, i32* %c, align 4
   ret i32 %v
 }
 
 ; Can we sink for different base if there is phi for base but not valid one?
 ; Both addresses are in the same block.
loop:
   br i1 %cond, label %if.then, label %fallthrough
 
 if.then:
   %a2 = getelementptr inbounds i64, i64* %b2, i64 5
   %c2 = bitcast i64* %a2 to i32*
   br label %fallthrough
 
 fallthrough:
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
   %c = phi i32* [%c3, %loop], [%c2, %if.then]
   %b = phi i64* [%b3, %loop], [%b2, %if.then]
   %v = load volatile i32, i32* %c, align 4
   %iv.inc = add i32 %iv, 1
   %cmp = icmp slt i32 %iv.inc, %N
   br i1 %cmp, label %loop, label %exit
 
 exit:

llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode.ll

 ; RUN: opt -S -codegenprepare < %s | FileCheck %s
 
 target datalayout =
 "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-unknown-linux-gnu"
 
 @x = external global [1 x [2 x <4 x float>]]
 
 ; Can we sink single addressing mode computation to use?
 define void @test1(i1 %cond, i64* %base) {
 ; CHECK-LABEL: @test1
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
 entry:
   %addr = getelementptr inbounds i64, i64* %base, i64 5
   %casted = bitcast i64* %addr to i32*
   br i1 %cond, label %if.then, label %fallthrough
 
 if.then:
   %v = load i32, i32* %casted, align 4
   br label %fallthrough

 ; CHECK-LABEL: @test2
 entry:
   %addr = getelementptr inbounds i64, i64* %base, i64 5
   %casted = bitcast i64* %addr to i32*
   br i1 %cond, label %if.then, label %fallthrough
 
 if.then:
 ; CHECK-LABEL: if.then:
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
   %v1 = load i32, i32* %casted, align 4
   call void @foo(i32 %v1)
   %cmp = icmp eq i32 %v1, 0
   br i1 %cmp, label %next, label %fallthrough
 
 next:
 ; CHECK-LABEL: next:
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
   %v2 = load i32, i32* %casted, align 4
   call void @foo(i32 %v2)
   br label %fallthrough
 
 fallthrough:
   ret void
 }
 
 ; If we have two loads in the same block, only need one copy of addressing mode
 ; - instruction selection will duplicate if needed
 define void @test3(i1 %cond, i64* %base) {
 ; CHECK-LABEL: @test3
 entry:
   %addr = getelementptr inbounds i64, i64* %base, i64 5
   %casted = bitcast i64* %addr to i32*
   br i1 %cond, label %if.then, label %fallthrough
 
 if.then:
 ; CHECK-LABEL: if.then:
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
   %v1 = load i32, i32* %casted, align 4
   call void @foo(i32 %v1)
-; CHECK-NOT: getelementptr i8, {{.+}} 40
+; CHECK-NOT: getelementptr inbounds i8, {{.+}} 40
   %v2 = load i32, i32* %casted, align 4
   call void @foo(i32 %v2)
   br label %fallthrough
 
 fallthrough:
   ret void
 }
 
 ; Can we still sink addressing mode if there's a cold use of the
 ; address itself?  
 define void @test4(i1 %cond, i64* %base) {
 ; CHECK-LABEL: @test4
 entry:
   %addr = getelementptr inbounds i64, i64* %base, i64 5
   %casted = bitcast i64* %addr to i32*
   br i1 %cond, label %if.then, label %fallthrough
 
 if.then:
 ; CHECK-LABEL: if.then:
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
   %v1 = load i32, i32* %casted, align 4
   call void @foo(i32 %v1)
   %cmp = icmp eq i32 %v1, 0
   br i1 %cmp, label %rare.1, label %fallthrough
 
 fallthrough:
   ret void
 
 rare.1:
 ; CHECK-LABEL: rare.1:
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
   call void @slowpath(i32 %v1, i32* %casted) cold
   br label %fallthrough
 }
 
 ; Negative test - don't want to duplicate addressing into hot path
 define void @test5(i1 %cond, i64* %base) {
 ; CHECK-LABEL: @test5
 entry:
-; CHECK: %addr = getelementptr
+; CHECK: %addr = getelementptr inbounds
   %addr = getelementptr inbounds i64, i64* %base, i64 5
   %casted = bitcast i64* %addr to i32*
   br i1 %cond, label %if.then, label %fallthrough
 
 if.then:
 ; CHECK-LABEL: if.then:
-; CHECK-NOT: getelementptr i8, {{.+}} 40
+; CHECK-NOT: getelementptr inbounds i8, {{.+}} 40
   %v1 = load i32, i32* %casted, align 4
   call void @foo(i32 %v1)
   %cmp = icmp eq i32 %v1, 0
   br i1 %cmp, label %rare.1, label %fallthrough
 
 fallthrough:
   ret void
 
 rare.1:
   call void @slowpath(i32 %v1, i32* %casted) ;; NOT COLD
   br label %fallthrough
 }
 
 ; Negative test - opt for size
 define void @test6(i1 %cond, i64* %base) minsize {
 ; CHECK-LABEL: @test6
 entry:
 ; CHECK: %addr = getelementptr
   %addr = getelementptr inbounds i64, i64* %base, i64 5
   %casted = bitcast i64* %addr to i32*
   br i1 %cond, label %if.then, label %fallthrough
 
 if.then:
 ; CHECK-LABEL: if.then:
-; CHECK-NOT: getelementptr i8, {{.+}} 40
+; CHECK-NOT: getelementptr inbounds i8, {{.+}} 40
   %v1 = load i32, i32* %casted, align 4
   call void @foo(i32 %v1)
   %cmp = icmp eq i32 %v1, 0
   br i1 %cmp, label %rare.1, label %fallthrough
 
 fallthrough:
   ret void
 

 ; CHECK-LABEL: @test7
 entry:
   %addr = getelementptr inbounds i64, i64* %base, i64 5
   %casted = bitcast i64* %addr to i32*
   br i1 %cond, label %if.then, label %fallthrough
 
 if.then:
 ; CHECK-LABEL: if.then:
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
   %v1 = load i32, i32* %casted, align 4
   call void @foo(i32 %v1)
   %cmp = icmp eq i32 %v1, 0
   br i1 %cmp, label %rare.1, label %next
 
 next:
 ; CHECK-LABEL: next:
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
   %v2 = load i32, i32* %casted, align 4
   call void @foo(i32 %v2)
   %cmp2 = icmp eq i32 %v2, 0
   br i1 %cmp2, label %rare.1, label %fallthrough
 
 fallthrough:
   ret void
 
 rare.1:
 ; CHECK-LABEL: rare.1:
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
   call void @slowpath(i32 %v1, i32* %casted) cold
   br label %next
 
 rare.2:
 ; CHECK-LABEL: rare.2:
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
   call void @slowpath(i32 %v2, i32* %casted) cold
   br label %fallthrough
 }
 
 declare void @slowpath(i32, i32*)
 
 ; Make sure we don't end up in an infinite loop after we fail to sink.
 ; CHECK-LABEL: define void @test8

 if.then:
   call void @foo(i32 %iv)
   %addr.1 = getelementptr inbounds i64, i64* %base, i64 5
   %casted.1 = bitcast i64* %addr.1 to i32*
   br label %backedge
 
 backedge:
 ; CHECK-LABEL: backedge:
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
   %casted.merged = phi i32* [%casted.loop, %header], [%casted.1, %if.then]
   %v = load i32, i32* %casted.merged, align 4
   call void @foo(i32 %v)
   %iv.inc = add i32 %iv, 1
   %cmp = icmp slt i32 %iv.inc, 1000
   br i1 %cmp, label %header, label %exit
 
 exit:
   ret void
 }
 
 ; Make sure we can eliminate a select when both arguments perform equivalent
 ; address computation.
 define void @test10(i1 %cond, i64* %base) {
 ; CHECK-LABEL: @test10
-; CHECK: getelementptr i8, {{.+}} 40
+; CHECK: getelementptr inbounds i8, {{.+}} 40
 ; CHECK-NOT: select
 entry:
   %gep1 = getelementptr inbounds i64, i64* %base, i64 5
   %gep1.casted = bitcast i64* %gep1 to i32*
   %base.casted = bitcast i64* %base to i32*
   %gep2 = getelementptr inbounds i32, i32* %base.casted, i64 10
   %casted.merged = select i1 %cond, i32* %gep1.casted, i32* %gep2
   %v = load i32, i32* %casted.merged, align 4

llvm/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll

 ; RUN: opt -S -codegenprepare < %s | FileCheck %s -check-prefix=CHECK -check-prefix=GEP
 
 target datalayout =
 "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-unknown-linux-gnu"
 
 ; CHECK-LABEL: @load_cast_gep
 ; GEP: [[CAST:%[0-9]+]] = addrspacecast i64* %base to i8 addrspace(1)*
-; GEP: getelementptr i8, i8 addrspace(1)* [[CAST]], i64 40
+; GEP: getelementptr inbounds i8, i8 addrspace(1)* [[CAST]], i64 40
 define void @load_cast_gep(i1 %cond, i64* %base) {
 entry:
   %addr = getelementptr inbounds i64, i64* %base, i64 5
   %casted = addrspacecast i64* %addr to i32 addrspace(1)*
   br i1 %cond, label %if.then, label %fallthrough
 
 if.then:
   %v = load i32, i32 addrspace(1)* %casted, align 4
   br label %fallthrough
 
 fallthrough:
   ret void
 }
 
 ; CHECK-LABEL: @store_gep_cast
 ; GEP: [[CAST:%[0-9]+]] = addrspacecast i64* %base to i8 addrspace(1)*
-; GEP: getelementptr i8, i8 addrspace(1)* [[CAST]], i64 20
+; GEP: getelementptr inbounds i8, i8 addrspace(1)* [[CAST]], i64 20
 define void @store_gep_cast(i1 %cond, i64* %base) {
 entry:
   %casted = addrspacecast i64* %base to i32 addrspace(1)*
   %addr = getelementptr inbounds i32, i32 addrspace(1)* %casted, i64 5
   br i1 %cond, label %if.then, label %fallthrough
 
 if.then:
   store i32 0, i32 addrspace(1)* %addr, align 4
   br label %fallthrough
 
 fallthrough:
   ret void
 }