[X86] Allow 8-bit INC/DEC to be converted to LEA.

[craig.topper]

Summary

We already do this for 16/32/64 as well as 8-bit add with register/immediate. Might as well do it for 8-bit INC/DEC too.

[RKSimon]

Are we going to end up with issues with cpus with slow/fast increment vs slow/fast lea?

[craig.topper]

INC is probably never faster than add. Just smaller. And we already convert adds to lea. And we already do this for other sizes of INC. So it shouldn’t create a new issue from that perspective.

[spatel]

Side note/follow-up from D58412 - in a local experiment, I removed 'FeatureSlowIncDec' from the default/generic x86-64 CPU model, and saw no regression test diffs. So I assume we're already converting to LEA in most cases already. As seen in some of the diffs here, that's probably for the best since it allows getting rid of an explicit mov register instruction?

[craig.topper]

There aren’t many tests that use x86-64 as a cpu are there? It’s not the default cpu in llc for 64-bit. Just in clang

[spatel]

In D58869#1416175, @craig.topper wrote:

There aren’t many tests that use x86-64 as a cpu are there? It’s not the default cpu in llc for 64-bit. Just in clang

Oh, I misunderstood how that gets set then. No, there aren't many tests that are explicitly setting -mcpu=generic. A grep shows 169 RUN lines with that string. So that seems weird...shouldn't we be testing the common case by default?

[craig.topper]

llc always uses "generic" as the cpu by default. With some special code to force "sse2" on 64-bit. Clang makes a platform specific decision. "pentium4" and "x86-64" are the 32-bit and 64-bit defaults for linux. Macs default to "yonah" and "core2" for 32-bit and 64-bit respectively. Less sure about other platforms. These are intended to enable mininum ISAs, but are also affecting our tuning decisions.

We should maybe look into making more tuning cpus for clang to use. Or we should support -mtune. So we can have separate default ISAs and tuning flags.

[spatel]

LGTM - the generic CPU concern is independent of this change, and as noted this is just making the logic more uniform. If there's some case where 'inc' is better, that should likely apply to all legal scalar types.

[RKSimon]

LGTM

llvm/trunk/lib/Target/X86/X86InstrArithmetic.td

def X86sub_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs),
                                (X86sub_flag node:$lhs, node:$rhs), [{
   // Only use DEC if the result is used.
   return !SDValue(N, 0).use_empty() && hasNoCarryFlagUses(SDValue(N, 1));
 }]>;
 
 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
 let Defs = [EFLAGS] in {
 let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
-let CodeSize = 2 in
+let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA.
 def INC8r  : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
                "inc{b}\t$dst",
                [(set GR8:$dst, EFLAGS, (X86add_flag_nocf GR8:$src1, 1))]>;
-let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA.
 def INC16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
                "inc{w}\t$dst",
                [(set GR16:$dst, EFLAGS, (X86add_flag_nocf GR16:$src1, 1))]>,
                OpSize16;
 def INC32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
                "inc{l}\t$dst",
                [(set GR32:$dst, EFLAGS, (X86add_flag_nocf GR32:$src1, 1))]>,
                OpSize32;

 let Predicates = [UseIncDec, In64BitMode] in {
   def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
                   [(store (add (loadi64 addr:$dst), 1), addr:$dst),
                    (implicit EFLAGS)]>;
 } // Predicates
 } // CodeSize = 2, SchedRW
 
 let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
-let CodeSize = 2 in
+let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA.
 def DEC8r  : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
                "dec{b}\t$dst",
                [(set GR8:$dst, EFLAGS, (X86sub_flag_nocf GR8:$src1, 1))]>;
-let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA.
 def DEC16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
                "dec{w}\t$dst",
                [(set GR16:$dst, EFLAGS, (X86sub_flag_nocf GR16:$src1, 1))]>,
                OpSize16;
 def DEC32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
                "dec{l}\t$dst",
                [(set GR32:$dst, EFLAGS, (X86sub_flag_nocf GR32:$src1, 1))]>,
                OpSize32;

llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
   switch (MIOpc) {
   default: llvm_unreachable("Unreachable!");
   case X86::SHL16ri: {
     unsigned ShAmt = MI.getOperand(2).getImm();
     MIB.addReg(0).addImm(1ULL << ShAmt)
        .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
     break;
   }
+  case X86::INC8r:
   case X86::INC16r:
     addRegOffset(MIB, InRegLEA, true, 1);
     break;
+  case X86::DEC8r:
   case X86::DEC16r:
     addRegOffset(MIB, InRegLEA, true, -1);
     break;
   case X86::ADD8ri:
   case X86::ADD8ri_DB:
   case X86::ADD16ri:
   case X86::ADD16ri8:
   case X86::ADD16ri_DB:
MachineInstrBuilder MIB =
             .add(Dest)
             .addReg(SrcReg, getKillRegState(isKill));
     if (ImplicitOp.getReg() != 0)
       MIB.add(ImplicitOp);
 
     NewMI = addOffset(MIB, 1);
     break;
   }
-  case X86::INC16r:
-    return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
   case X86::DEC64r:
   case X86::DEC32r: {
     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
         : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
 
     bool isKill;
     unsigned SrcReg;
     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
                         ImplicitOp, LV))
       return nullptr;
 
     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
                                   .add(Dest)
                                   .addReg(SrcReg, getKillRegState(isKill));
     if (ImplicitOp.getReg() != 0)
       MIB.add(ImplicitOp);
 
     NewMI = addOffset(MIB, -1);
 
     break;
   }
+  case X86::DEC8r:
+  case X86::INC8r:
+    Is8BitOp = true;
+    LLVM_FALLTHROUGH;
   case X86::DEC16r:
+  case X86::INC16r:
     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
   case X86::ADD64rr:
   case X86::ADD64rr_DB:
   case X86::ADD32rr:
   case X86::ADD32rr_DB: {
     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
     unsigned Opc;
     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)

llvm/trunk/test/CodeGen/X86/MergeConsecutiveStores.ll

 ; BWON-LABEL: loadStoreBaseIndexOffsetSextNoSex:
 ; BWON:       # %bb.0:
 ; BWON-NEXT:    movl %ecx, %r8d
 ; BWON-NEXT:    xorl %ecx, %ecx
 ; BWON-NEXT:    .p2align 4, 0x90
 ; BWON-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
 ; BWON-NEXT:    movsbq (%rdi,%rcx), %rax
 ; BWON-NEXT:    movzbl (%rdx,%rax), %r9d
-; BWON-NEXT:    incb %al
+; BWON-NEXT:    leal 1(%rax), %eax
 ; BWON-NEXT:    movsbq %al, %rax
 ; BWON-NEXT:    movzbl (%rdx,%rax), %eax
 ; BWON-NEXT:    movb %r9b, (%rsi,%rcx,2)
 ; BWON-NEXT:    movb %al, 1(%rsi,%rcx,2)
 ; BWON-NEXT:    incq %rcx
 ; BWON-NEXT:    cmpl %ecx, %r8d
 ; BWON-NEXT:    jne .LBB12_1
 ; BWON-NEXT:  # %bb.2:
 ; BWON-NEXT:    retq
 ;
 ; BWOFF-LABEL: loadStoreBaseIndexOffsetSextNoSex:
 ; BWOFF:       # %bb.0:
 ; BWOFF-NEXT:    movl %ecx, %r8d
 ; BWOFF-NEXT:    xorl %ecx, %ecx
 ; BWOFF-NEXT:    .p2align 4, 0x90
 ; BWOFF-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
 ; BWOFF-NEXT:    movsbq (%rdi,%rcx), %rax
 ; BWOFF-NEXT:    movb (%rdx,%rax), %r9b
-; BWOFF-NEXT:    incb %al
+; BWOFF-NEXT:    leal 1(%rax), %eax
 ; BWOFF-NEXT:    movsbq %al, %rax
 ; BWOFF-NEXT:    movb (%rdx,%rax), %al
 ; BWOFF-NEXT:    movb %r9b, (%rsi,%rcx,2)
 ; BWOFF-NEXT:    movb %al, 1(%rsi,%rcx,2)
 ; BWOFF-NEXT:    incq %rcx
 ; BWOFF-NEXT:    cmpl %ecx, %r8d
 ; BWOFF-NEXT:    jne .LBB12_1
 ; BWOFF-NEXT:  # %bb.2:

llvm/trunk/test/CodeGen/X86/copy-eflags.ll

 ; X32-NEXT:    calll external
 ; X32-NEXT:    addl $4, %esp
 ; X32-NEXT:  .LBB0_2: # %if.end
 ; X32-NEXT:    xorl %eax, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test1:
 ; X64:       # %bb.0: # %entry
-; X64-NEXT:    movb {{.*}}(%rip), %dil
-; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    incb %al
+; X64-NEXT:    movb {{.*}}(%rip), %cl
+; X64-NEXT:    leal 1(%rcx), %eax
 ; X64-NEXT:    movb %al, {{.*}}(%rip)
 ; X64-NEXT:    incl {{.*}}(%rip)
-; X64-NEXT:    sete %sil
-; X64-NEXT:    movb {{.*}}(%rip), %cl
-; X64-NEXT:    movl %ecx, %edx
-; X64-NEXT:    incb %dl
-; X64-NEXT:    cmpb %dil, %cl
+; X64-NEXT:    sete %dl
+; X64-NEXT:    movb {{.*}}(%rip), %sil
+; X64-NEXT:    leal 1(%rsi), %edi
+; X64-NEXT:    cmpb %cl, %sil
 ; X64-NEXT:    sete {{.*}}(%rip)
-; X64-NEXT:    movb %dl, {{.*}}(%rip)
-; X64-NEXT:    testb %sil, %sil
+; X64-NEXT:    movb %dil, {{.*}}(%rip)
+; X64-NEXT:    testb %dl, %dl
 ; X64-NEXT:    jne .LBB0_2
 ; X64-NEXT:  # %bb.1: # %if.then
 ; X64-NEXT:    pushq %rax
 ; X64-NEXT:    movsbl %al, %edi
 ; X64-NEXT:    callq external
 ; X64-NEXT:    addq $8, %rsp
 ; X64-NEXT:  .LBB0_2: # %if.end
 ; X64-NEXT:    xorl %eax, %eax